From 17db582341e66bab1dec6cea351c026595324cc4 Mon Sep 17 00:00:00 2001 From: philipp Date: Fri, 6 Aug 2021 13:07:30 +0200 Subject: [PATCH] Making aiger a class Aiger circuits noew have their own class. Monitors can be translated to and obtained from aiger circuits. Moreover a step by step evaluation method is provided. * spot/twaalgos/aiger.hh, spot/twaalgos/aiger.cc: Here * bin/ltlsynt.cc: Adopt new modes * tests/core/ltlsynt.test: Adapt tests * python/spot/impl.i: Add python support * tests/Makefile.am, tests/python/aiger.py: New test cases --- bin/ltlsynt.cc | 13 +- python/spot/impl.i | 3 + spot/twaalgos/aiger.cc | 2471 +++++++++++++++++++++------- spot/twaalgos/aiger.hh | 457 +++++- tests/Makefile.am | 1 + tests/core/ltlsynt.test | 187 ++- tests/python/aiger.py | 3388 +++++++++++++++++++++++++++++++++++++++ 7 files changed, 5865 insertions(+), 655 deletions(-) create mode 100644 tests/python/aiger.py diff --git a/bin/ltlsynt.cc b/bin/ltlsynt.cc index 7b332dc18..948376601 100644 --- a/bin/ltlsynt.cc +++ b/bin/ltlsynt.cc @@ -92,10 +92,13 @@ static const argp_option options[] = "print the parity game in the HOA format, do not solve it", 0}, { "realizability", OPT_REAL, nullptr, 0, "realizability only, do not compute a winning strategy", 0}, - { "aiger", OPT_PRINT_AIGER, "ITE|ISOP", OPTION_ARG_OPTIONAL, - "prints a winning strategy as an AIGER circuit. With argument \"ISOP\"" - " conditions are converted to DNF, while the default \"ITE\" uses the " - "if-the-else normal form.", 0}, + { "aiger", OPT_PRINT_AIGER, "ite|isop|both[+ud][+dc]" + "[+sub0|sub1|sub2]", OPTION_ARG_OPTIONAL, + "prints a winning strategy as an AIGER circuit. The first, and only " + "mandatory options defines the method to be used. ite for If-then-else " + "normal form, isop for irreducible sum of producs. Both tries both" + "encodings and keeps the smaller one. The other options further " + "refine the encoding, see aiger:::encode_bdd.", 0}, { "verbose", OPT_VERBOSE, nullptr, 0, "verbose mode", -1 }, { "csv", OPT_CSV, "[>>]FILENAME", OPTION_ARG_OPTIONAL, @@ -563,7 +566,7 @@ parse_opt(int key, char* arg, struct argp_state*) opt_print_hoa_args = arg; break; case OPT_PRINT_AIGER: - opt_print_aiger = arg ? arg : "INF"; + opt_print_aiger = arg ? arg : "isop"; break; case OPT_REAL: opt_real = true; diff --git a/python/spot/impl.i b/python/spot/impl.i index dbe2ccf48..1e7497244 100644 --- a/python/spot/impl.i +++ b/python/spot/impl.i @@ -60,6 +60,7 @@ %shared_ptr(spot::emptiness_check) %shared_ptr(spot::emptiness_check_instantiator) %shared_ptr(spot::tgbasl) +%shared_ptr(spot::aig) %import "buddy.i" @@ -109,6 +110,7 @@ #include #include +#include #include #include #include @@ -619,6 +621,7 @@ def state_is_accepting(self, src) -> "bool": // Should come after the definition of twa_graph +%include %include %include %include diff --git a/spot/twaalgos/aiger.cc b/spot/twaalgos/aiger.cc index ff73e7a58..78ca35f58 100644 --- a/spot/twaalgos/aiger.cc +++ b/spot/twaalgos/aiger.cc @@ -1,5 +1,5 @@ // -*- coding: utf-8 -*- -// Copyright (C) 2017-2020 Laboratoire de Recherche et Développement +// Copyright (C) 2017-2021 Laboratoire de Recherche et Développement // de l'Epita (LRDE). // // This file is part of Spot, a model checking library. @@ -25,679 +25,1936 @@ #include #include #include +#include +#include +#include +#include +#include #include #include #include +#include + +#define STR(x) #x +#define STR_(x) STR(x) +#define STR_LINE STR_(__LINE__) + +namespace +{ + using namespace spot; + + static std::vector + name_vector(unsigned n, const std::string& prefix) + { + std::vector res; + for (unsigned i = 0; i != n; ++i) + res.push_back(prefix + std::to_string(i)); + return res; + } + + void check_double_names(std::vector sv, std::string msg) + { + if (sv.size() < 2) + return; + std::sort(sv.begin(), sv.end()); + const unsigned svs = sv.size() - 1; + for (unsigned i = 0; i < svs; ++i) + if (sv[i] == sv[i+1]) + throw std::runtime_error(msg + sv[i]); + } + + std::tuple, std::vector, + std::vector, + std::vector, + std::vector> + > + parse_aag_impl_(std::istream& iss, const std::string& filename) + { + + auto error_aig = [fn = filename](int line_src, + const std::string& msg, + unsigned line_file) + { + throw parse_error("spot/twaalgos/aiger.cc:" + std::to_string(line_src) + + ": in " + fn + " hit error: " + msg + + " at line " + std::to_string(line_file) + + ".\n"); + }; + + //results + std::vector input_names; + std::vector output_names; + std::vector latches; + std::vector outputs; + std::vector> gates; + + unsigned max_index, nb_inputs, nb_latches, nb_outputs, nb_and; + + std::string line; + getline(iss, line); + unsigned line_number = 1; + if (sscanf(line.c_str(), "aag %u %u %u %u %u", &max_index, &nb_inputs, + &nb_latches, &nb_outputs, &nb_and) != 5) + error_aig(__LINE__, "invalid header", line_number); + + if (max_index < nb_inputs + nb_latches + nb_and) + error_aig(__LINE__, "More variables than indicated by max var", + line_number); + + latches.reserve(nb_latches); + outputs.reserve(nb_outputs); + gates.reserve(nb_and); + + for (unsigned i = 0; i < nb_inputs; ++i) + { + if (!iss) + error_aig(__LINE__, "missing input", line_number); + + line.clear(); + getline(iss, line); + if ((unsigned)std::stoi(line) != 2*(i+1)) + error_aig(__LINE__, "invalid input numbering for input nbr " + + std::to_string(i), line_number); + ++line_number; + } + for (unsigned i = 0; i < nb_latches; ++i) + { + if (!iss) + error_aig(__LINE__, "missing latch", line_number); + + line.clear(); + getline(iss, line); + ++line_number; + unsigned latch_var, next_state; + if (sscanf(line.c_str(), "%u %u", &latch_var, &next_state) != 2) + error_aig(__LINE__, "invalid latch", line_number); + if (latch_var != 2*(1 + nb_inputs + i)) + error_aig(__LINE__, "invalid latch numbering", line_number); + + latches.push_back(next_state); + } + for (unsigned i = 0; i < nb_outputs; ++i) + { + if (!iss) + error_aig(__LINE__, "missing output", line_number); + + line.clear(); + getline(iss, line); + ++line_number; + unsigned num_out; + if (sscanf(line.c_str(), "%u", &num_out) != 1) + error_aig(__LINE__, "invalid output definition", line_number); + outputs.push_back(num_out); + } + for (unsigned i = 0; i < nb_and; ++i) + { + unsigned and_gate, lhs, rhs; + if (!iss) + error_aig(__LINE__, "missing AND", line_number); + line.clear(); + getline(iss, line); + ++line_number; + if (sscanf(line.c_str(), "%u %u %u", &and_gate, &lhs, &rhs) != 3) + error_aig(__LINE__, "invalid AND", line_number); + if (and_gate != 2*(1 + nb_inputs + nb_latches + i)) + error_aig(__LINE__, "invalid gate numbering. Expected " + + std::to_string((2*(1 + nb_inputs + nb_latches + i))) + + " got " + std::to_string(and_gate), line_number); + gates.emplace_back(lhs, rhs); + } + line.clear(); + + getline(iss, line); + ++line_number; + bool comment_sec = false; + while (iss && !comment_sec) + { + unsigned pos_var_name; + char first_char = line[0]; + char var_name[256]; + switch (first_char) + { + // latches names non supported + case 'l': + { + line.clear(); + getline(iss, line); + ++line_number; + continue; + } + case 'i': + { + if (sscanf(line.c_str(), "i%u %255s", &pos_var_name, var_name) != 2 + || pos_var_name >= nb_inputs) + error_aig(__LINE__, "could not parse input name: " + + line, line_number); + auto itn = std::find(input_names.begin(), input_names.end(), + var_name); + if (itn != input_names.end()) + error_aig(__LINE__, std::string("input name ") + var_name + + " appears twice", line_number); + input_names.push_back(var_name); + line.clear(); + getline(iss, line); + ++line_number; + break; + } + case 'o': + { + if (sscanf(line.c_str(), "o%u %255s", &pos_var_name, var_name) != 2 + || pos_var_name >= nb_outputs) + error_aig(__LINE__, "could not parse output name: " + + line, line_number); + auto itn = std::find(output_names.begin(), output_names.end(), + var_name); + if (itn != output_names.end()) + error_aig(__LINE__, std::string("output name ") + var_name + + " appears twice", line_number); + output_names.push_back(var_name); + line.clear(); + getline(iss, line); + ++line_number; + break; + } + case 'c': + { + comment_sec = true; + break; + } + default: + { + error_aig(__LINE__, "invalid line", line_number); + } + } + } + if ((not input_names.empty()) && (input_names.size() != nb_inputs)) + error_aig(__LINE__, "Either all or none of the inputs can be named", + 0); + else + input_names = name_vector(nb_inputs, "i"); + if ((not output_names.empty()) && (output_names.size() != nb_outputs)) + error_aig(__LINE__, "Either all or none of the outputs can be named", + 0); + else + output_names = name_vector(nb_outputs, "o"); + + return std::make_tuple(input_names, output_names, latches, outputs, gates); + } +} namespace spot { - namespace + aig::aig(const std::vector& inputs, + const std::vector& outputs, + unsigned num_latches, + bdd_dict_ptr dict) + : num_inputs_(inputs.size()), + num_outputs_(outputs.size()), + num_latches_(num_latches), + input_names_(inputs), + output_names_(outputs), + max_var_((inputs.size() + num_latches) * 2), + next_latches_(num_latches, -1u), + outputs_(outputs.size(), -1u), + dict_{dict} { - static std::vector - name_vector(unsigned n, const std::string& prefix) + // check that in/out names are unique + check_double_names(inputs, "spot/twaalgos/aiger.cc:" STR_LINE ": input" + " name appears multiple times: "); + check_double_names(outputs, "spot/twaalgos/aiger.cc:" STR_LINE ": output" + " name appears multiple times: "); + + bdd2var_[bddtrue.id()] = aig_true(); + var2bdd_[aig_true()] = bddtrue; + bdd2var_[bddfalse.id()] = aig_false(); + var2bdd_[aig_false()] = bddfalse; + + all_ins_ = bddtrue; + all_latches_ = bddtrue; + + l0_ = dict_->register_anonymous_variables(num_latches_, this); + for (unsigned i = 0; i < num_latches_; ++i) + { + bdd b = bdd_ithvar(l0_+i); + register_latch_(i, b); + all_latches_ &= b; + } + + unsigned i = 0; + for (auto& in : input_names_) { - std::vector res(n); - for (unsigned i = 0; i != n; ++i) - res[i] = prefix + std::to_string(i); - return res; + bdd b = bdd_ithvar(dict_->register_proposition(formula::ap(in), this)); + register_input_(i, b); + all_ins_ &= b; + ++i; } + for (auto& out : output_names_) + dict_->register_proposition(formula::ap(out), this); - // A class to represent an AIGER circuit - class aig - { - private: - unsigned max_var_; - unsigned num_inputs_; - unsigned num_latches_; - unsigned num_outputs_; + bdd2var_.reserve(4 * (num_inputs_ + num_outputs_ + num_latches_)); + var2bdd_.reserve(4 * (num_inputs_ + num_outputs_ + num_latches_)); + } - std::vector latches_; - std::vector outputs_; - std::vector input_names_; - std::vector output_names_; - std::vector> and_gates_; - // Cache the function computed by each variable as a bdd. - std::unordered_map var2bdd_; - std::unordered_map bdd2var_; + /// \brief Constructing the circuit with generic names. + aig::aig(unsigned num_inputs, unsigned num_outputs, + unsigned num_latches, bdd_dict_ptr dict) + : aig(name_vector(num_inputs, "in"), + name_vector(num_outputs, "out"), num_latches, dict) + { + } - public: - aig(const std::vector& inputs, - const std::vector& outputs, - unsigned num_latches) - : max_var_((inputs.size() + num_latches)*2), - num_inputs_(inputs.size()), - num_latches_(num_latches), - num_outputs_(outputs.size()), - latches_(num_latches), - outputs_(outputs.size()), - input_names_(inputs), - output_names_(outputs) + // register the bdd corresponding the an + // aig literal + void aig::register_new_lit_(unsigned v, const bdd& b) + { + assert(!var2bdd_.count(v) || var2bdd_.at(v) == b); + assert(!bdd2var_.count(b.id()) || bdd2var_.at(b.id()) == v); + var2bdd_[v] = b; + bdd2var_[b.id()] = v; + // Also store negation + // Do not use aig_not as tests will fail + var2bdd_[v ^ 1] = !b; + bdd2var_[(!b).id()] = v ^ 1; + } + + void aig::register_latch_(unsigned i, const bdd& b) + { + register_new_lit_(latch_var(i), b); + } + + void aig::register_input_(unsigned i, const bdd& b) + { + register_new_lit_(input_var(i), b); + } + + // Unregisters positive and negative form of a literal + // which has to be given in positive form + void aig::unregister_lit_(unsigned v) + { + assert(((v&1) == 0) && "Expected positive form"); + unsigned n_del; + n_del = bdd2var_.erase(var2bdd_[v].id()); + assert(n_del); + n_del = var2bdd_.erase(v); + assert(n_del); + v = v ^ 1; + n_del = bdd2var_.erase(var2bdd_[v].id()); + assert(n_del); + n_del = var2bdd_.erase(v); + assert(n_del); + } + + // Get propositions that are commun to all + // possible products so that they can be anded at the end + bdd aig::accum_common_(const bdd& b) const + { + bdd commun_bdd = bddtrue; + for (unsigned i = 0; i < num_inputs(); ++i) { - bdd2var_[bddtrue] = 1; - var2bdd_[1] = bddtrue; - bdd2var_[bddfalse] = 0; - var2bdd_[0] = bddfalse; - - bdd2var_.reserve(4 * (num_inputs_ + num_latches_)); - var2bdd_.reserve(4 * (num_inputs_ + num_latches_)); + if (bdd_implies(b, input_bdd(i))) + commun_bdd &= input_bdd(i); + else if (bdd_implies(b, input_bdd(i, true))) + commun_bdd &= input_bdd(i, true); } - - aig(unsigned num_inputs, unsigned num_latches, unsigned num_outputs) - : aig(name_vector(num_inputs, "in"), name_vector(num_outputs, "out"), - num_latches) + for (unsigned i = 0; i < num_latches(); ++i) { + if (bdd_implies(b, latch_bdd(i))) + commun_bdd &= latch_bdd(i); + else if (bdd_implies(b, latch_bdd(i, true))) + commun_bdd &= latch_bdd(i, true); } + assert(commun_bdd != bddfalse); + return commun_bdd; + } - // register the bdd corresponding the an - // aig literal - inline void register_new_lit(unsigned v, const bdd& b) + void aig::split_cond_(const bdd& b, char so_mode, + std::vector& cond_parts) + { + cond_parts.clear(); + switch (so_mode) { - assert(!var2bdd_.count(v) || var2bdd_.at(v) == b); - assert(!bdd2var_.count(b) || bdd2var_.at(b) == v); - var2bdd_[v] = b; - bdd2var_[b] = v; - // Also store negation - // Do not use aig_not as tests will fail - var2bdd_[v ^ 1] = !b; - bdd2var_[!b] = v ^ 1; + case 0: + { + cond_parts.push_back(b); + return; + } + case 1: + { + assert(bdd_is_cube(b)); + auto push = [&](const bdd& bb) + { + assert(bb != bddfalse); + if (bb != bddtrue) + cond_parts.push_back(bb); + }; + // Break the bdd into latches/inputs/gates + push(bdd_existcomp(b, all_latches_)); // Only latches + push(bdd_existcomp(b, all_ins_)); // Only inputs + push(bdd_exist(bdd_exist(b, all_ins_), all_latches_)); // Only gates + return; //Done + } + case 2: + { + bdd common = accum_common_(b); + if (common != bddtrue) + { + cond_parts.push_back(common); + cond_parts.push_back(bdd_exist(b, common)); + } + else + cond_parts.push_back(b); + return; //Done + } + default: + throw std::runtime_error("Unrecognised option for encode_bdd."); } + } - inline unsigned input_var(unsigned i) const + aig::safe_point aig::get_safe_point_() const + { + return {max_var_, and_gates_.size()}; + } + + aig::safe_stash + aig::roll_back_(safe_point sf, bool do_stash) + { + // todo specialise for safe_all? + safe_stash ss; + auto& [gates, vardict, negs] = ss; + if (do_stash) { - assert(i < num_inputs_); - return (1 + i) * 2; + unsigned dn = max_var_ - sf.first; + assert((dn&1) == 0); + dn /= 2; + assert((int) dn == std::distance(and_gates_.begin()+sf.second, + and_gates_.end())); + gates.resize(dn); + vardict.reserve(dn); + negs.reserve(dn); + //Copy and erase the lits + for (unsigned v = sf.first+2; v <= max_var_; v += 2) + { + vardict.emplace_back(v, var2bdd_[v]); + negs.push_back(var2bdd_[v+1]); + } + // Copy the gates + std::copy(and_gates_.begin()+sf.second, and_gates_.end(), + gates.begin()); } + // 1 Delete all literals + // max_var_old was used before + // max_var_ is currently used + for (unsigned v = sf.first+2; v <= max_var_; v += 2) + unregister_lit_(v); + // 2 Set back the gates + and_gates_.erase(and_gates_.begin()+sf.second, and_gates_.end()); + max_var_ = sf.first; + return ss; + } - inline unsigned latch_var(unsigned i) + void + aig::reapply_(safe_point sf, const safe_stash& ss) + { + // Do some check_ups + auto& [gates, vardict, _] = ss; + assert(gates.size() == vardict.size()); + assert(sf.first == max_var_); + assert(sf.second == and_gates_.size()); + unsigned new_max_var_ = max_var_ + gates.size()*2; + for (auto& p : vardict) { - assert(i < latches_.size()); - return (1 + num_inputs_ + i) * 2; + assert(max_var_ + 1 < p.first); + assert(p.first <= new_max_var_+1); + register_new_lit_(p.first, p.second); } + and_gates_.insert(and_gates_.end(), + gates.begin(), gates.end()); + max_var_ = new_max_var_; + } - inline unsigned gate_var(unsigned i)const - { - assert(i < and_gates_.size()); - return (1 + num_inputs_ + num_latches_ + i) * 2; - } + void aig::set_output(unsigned i, unsigned v) + { + assert(v <= max_var() + 1); + outputs_[i] = v; + } - void set_output(unsigned i, unsigned v) - { - assert(v <= max_var_+1); - outputs_[i] = v; - } + void aig::set_next_latch(unsigned i, unsigned v) + { + assert(v <= max_var() + 1); + next_latches_[i] = v; + } - void set_latch(unsigned i, unsigned v) - { - assert(v <= max_var_+1); - latches_[i] = v; - } + unsigned aig::aig_not(unsigned v) + { + unsigned not_v = v ^ 1; + assert(var2bdd_.count(v) && var2bdd_.count(not_v)); + return not_v; + } - unsigned aig_true() const - { - return 1; - } + unsigned aig::aig_and(unsigned v1, unsigned v2) + { + assert(var2bdd_.count(v1)); + assert(var2bdd_.count(v2)); - unsigned aig_false() const + if (v1 != v2) { - return 0; - } - - unsigned aig_not(unsigned v) - { - unsigned not_v = v ^ 1; - assert(var2bdd_.count(v) - && var2bdd_.count(not_v)); - return not_v; - } - - unsigned aig_and(unsigned v1, unsigned v2) - { - assert(var2bdd_.count(v1)); - assert(var2bdd_.count(v2)); bdd b = var2bdd_[v1] & var2bdd_[v2]; - auto it = bdd2var_.find(b); - if (it != bdd2var_.end()) + auto [it, inserted] = bdd2var_.try_emplace(b.id(), 0); + if (!inserted) return it->second; max_var_ += 2; + it->second = max_var_; and_gates_.emplace_back(v1, v2); - register_new_lit(max_var_, b); + register_new_lit_(max_var_, b); return max_var_; } + else + return v1; + } - unsigned aig_and(std::vector vs) + unsigned aig::aig_and(std::vector& vs) + { + // Note: we could check if some if the variables + // correspond to true or false. + // However this never happens during automatic construction, + // so it would be useless overhead in most cases + std::sort(vs.begin(), vs.end()); + auto new_end = std::unique(vs.begin(), vs.end()); + vs.erase(new_end, vs.end()); + + if (vs.empty()) + return aig_true(); + if (vs.size() == 1) + return vs[0]; + if (vs.size() == 2) + return aig_and(vs[0], vs[1]); + + unsigned add_elem = -1u; + do { - if (vs.empty()) - return aig_true(); - if (vs.size() == 1) - return vs[0]; - if (vs.size() == 2) - return aig_and(vs[0], vs[1]); - - do + if (vs.size() & 1) { - if (vs.size()&1) - // Odd size -> make even - vs.push_back(aig_true()); - // Sort to increase reusage gates - std::sort(vs.begin(), vs.end()); - // Reduce two by two inplace - for (unsigned i = 0; i < vs.size()/2; ++i) - vs[i] = aig_and(vs[2*i], vs[2*i + 1]); - vs.resize(vs.size()/2); - }while (vs.size() > 1); - return vs[0]; - } - - unsigned aig_or(unsigned v1, unsigned v2) - { - unsigned n1 = aig_not(v1); - unsigned n2 = aig_not(v2); - return aig_not(aig_and(n1, n2)); - } - - unsigned aig_or(std::vector vs) - { - for (unsigned i = 0; i < vs.size(); ++i) - vs[i] = aig_not(vs[i]); - return aig_not(aig_and(vs)); - } - - unsigned aig_pos(unsigned v) - { - return v & ~1; - } - - void remove_unused() - { - // Run a DFS on the gates to collect - // all nodes connected to the output. - std::vector todo; - std::vector used(and_gates_.size(), false); - - // The variables are numbered by first enumerating - // inputs, latches and finally the and-gates - // v_latch = (1+n_i+i)*2 if latch is in positive form - // if v/2 < 1+n_i -> v is an input - // v_gate = (1+n_i+n_l+i)*2 if gate is in positive form - // if v/2 < 1+n_i_nl -> v is a latch - auto v2idx = [&](unsigned v)->unsigned - { - assert(!(v & 1)); - const unsigned Nlatch_min = 1 + num_inputs_; - const unsigned Ngate_min = 1 + num_inputs_ + num_latches_; - - // Note: this will at most run twice - while (true) - { - unsigned i = v / 2; - if (i >= Ngate_min) - // v is a gate - return i - Ngate_min; - else if (i >= Nlatch_min) - // v is a latch -> get gate - v = aig_pos(latches_.at(i - Nlatch_min)); - else - // v is a input -> nothing to do - return -1U; - } - }; - - auto mark = [&](unsigned v) - { - unsigned idx = v2idx(aig_pos(v)); - if ((idx == -1U) || used[idx]) - return; - used[idx] = true; - todo.push_back(idx); - }; - - for (unsigned v : outputs_) - mark(v); - - while (!todo.empty()) - { - unsigned idx = todo.back(); - todo.pop_back(); - - mark(and_gates_[idx].first); - mark(and_gates_[idx].second); + // Odd size -> make even + add_elem = vs.back(); + vs.pop_back(); } - // Erase and_gates that were not seen in the above - // exploration. - // To avoid renumbering all gates, erasure is done - // by setting both inputs to "false" - for (unsigned idx = 0; idx < used.size(); ++idx) - if (!used[idx]) + + // Reduce two by two inplace + const unsigned idx_end = vs.size() / 2; + for (unsigned i = 0; i < idx_end; ++i) + vs[i] = aig_and(vs[2 * i], vs[2 * i + 1]); + vs.resize(vs.size() / 2); + // Add the odd elem if necessary + if (add_elem != -1u) + { + vs.push_back(add_elem); + add_elem = -1u; + } + // Sort to increase reusage gates + std::sort(vs.begin(), vs.end()); + } while (vs.size() > 1); + return vs[0]; + } + + unsigned aig::aig_or(unsigned v1, unsigned v2) + { + unsigned n1 = aig_not(v1); + unsigned n2 = aig_not(v2); + return aig_not(aig_and(n1, n2)); + } + + unsigned aig::aig_or(std::vector& vs) + { + std::transform(vs.begin(), vs.end(), vs.begin(), + [&](auto v){return aig_not(v); }); + vs[0] = aig_not(aig_and(vs)); + return vs[0]; + } + + unsigned aig::aig_pos(unsigned v) + { + return v & ~1; + } + unsigned aig::bdd2INFvar(const bdd& b) + { + // F = !v&low | v&high + // De-morgan + // !(!v&low | v&high) = !(!v&low) & !(v&high) + // !v&low | v&high = !(!(!v&low) & !(v&high)) + auto b_it = bdd2var_.find(b.id()); + if (b_it != bdd2var_.end()) + return b_it->second; + + // todo +// unsigned v_var = bdd2var_.at(bdd_var(b)); + unsigned v_var = bdd2var_.at(bdd_ithvar(bdd_var(b)).id()); + + unsigned b_branch_var[2] = {bdd2INFvar(bdd_low(b)), + bdd2INFvar(bdd_high(b))}; + + unsigned r = aig_not(aig_and(v_var, b_branch_var[1])); + unsigned l = aig_not(aig_and(aig_not(v_var), b_branch_var[0])); + return aig_not(aig_and(l, r)); + } + + unsigned aig::cube2var_(const bdd& b, const int use_split_off) + { + assert(bdd_is_cube(b) && "bdd is not a cube!"); + static std::vector parts_; + static std::vector prod_vars_; + static std::vector prod_parts_; + + parts_.clear(); + prod_vars_.clear(); + + split_cond_(b, use_split_off, parts_); + + decltype(bdd2var_)::const_iterator it; + for (bdd b : parts_) + { + prod_parts_.clear(); + while (b != bddtrue) + { + //Check if we know the sub-bdd + if ((it = bdd2var_.find(b.id())) != bdd2var_.end()) + { + // We already constructed prod + prod_parts_.push_back(it->second); + break; + } + // if the next lines failes, + // it is probably due to unregistered latches or ins + // todo +// unsigned v = bdd2var_.at(bdd_var(b)); + unsigned v = bdd2var_.at(bdd_ithvar(bdd_var(b)).id()); + if (bdd_high(b) == bddfalse) { - and_gates_[idx].first = 0; - and_gates_[idx].second = 0; + v = aig_not(v); + b = bdd_low(b); } + else + b = bdd_high(b); + prod_parts_.push_back(v); + } + prod_vars_.push_back(aig_and(prod_parts_)); + } + return aig_and(prod_vars_); + } + + unsigned aig::bdd2ISOPvar(const bdd& b, const int use_split_off) + { + static std::vector plus_vars_; + + auto it = bdd2var_.find(b.id()); + if (it != bdd2var_.end()) + return it->second; + + // Is it worth checking if it is a cube? + bdd prod; + minato_isop cond(b); + plus_vars_.clear(); + + while ((prod = cond.next()) != bddfalse) + plus_vars_.push_back(cube2var_(prod, + use_split_off == 2 ? 0 : use_split_off)); + + // Done building -> sum them + return aig_or(plus_vars_); + } + + unsigned aig::encode_bdd(const std::vector& c_alt, + char method, bool use_dual, + int use_split_off) + { + // Before doing anything else, let us check if one the variables + // already exists in which case we are done + for (const bdd& cond : c_alt) + { + auto it = bdd2var_.find(cond.id()); + if (it != bdd2var_.end()) + return it->second; } - // Takes a bdd, computes the corresponding literal - // using its DNF - unsigned bdd2DNFvar(const bdd& b, - const std::unordered_map& - bddvar_to_num) - { - std::vector plus_vars; - std::vector prod_vars(num_inputs_); + safe_point sf = get_safe_point_(); + + unsigned ngates_min = -1u; + safe_stash ss_min; + + unsigned res_var = -1u; + + std::vector used_m; + if (method == 0 || method == 2) + used_m.push_back(0); + if (method == 1 || method == 2) + used_m.push_back(1); + assert(used_m.size() + && "Can not convert the given method. " + "Only 0,1 and 2 are currently supported"); + + const auto negate = use_dual ? std::vector{false} + : std::vector{false, true}; + + auto enc_1 = [&](const bdd& b, + const char m) + { + return (m == 0) ? bdd2INFvar(b) + : bdd2ISOPvar(b, use_split_off != 2 + ? use_split_off : 0); + }; + + // we are given a list of "equivalent" bdds (we have to encode one of them + // but we can chose which one) + // We have different options: + // method, use_dual and use_split_off + // which can be arbitrarily combined + + std::vector cond_parts; + std::vector cond_vars; + for (bool do_negate : negate) + for (const bdd& b : c_alt) + { + bdd b_used = do_negate ? bdd_not(b) : b; + cond_parts.clear(); + split_cond_(b_used, + use_split_off != 1 ? use_split_off : 0, cond_parts); + + for (auto m : used_m) + { + cond_vars.clear(); + for (const bdd& cpart : cond_parts) + { + cond_vars.push_back(enc_1(cpart, m)); + if (num_gates() >= ngates_min) + break; // Can not be optimal + } + // Compute the and if there is still hope + unsigned this_res = -1u; + if (num_gates() < ngates_min) + this_res = aig_and(cond_vars); + + if (num_gates() < ngates_min) + { + // This is the new best + res_var = do_negate ? aig_not(this_res) : this_res; + ngates_min = num_gates(); + ss_min = roll_back_(sf, true); + } + else + // Reset the computations + roll_back_(sf, false); + } // Encoding styles + } // alternatives + // end do_negate + + // Reapply the best result + reapply_(sf, ss_min); + return res_var; + } + + + unsigned aig::encode_bdd(const bdd& b, + char method, bool use_dual, + int use_split_off) + { + return encode_bdd(std::vector{b}, method, use_dual, use_split_off); + } + + void aig::encode_all_bdds(const std::vector& all_bdd) + { + + // Build the set of all bdds needed in a "smart" way + // We only need the bdd or its negation, never both + std::set needed_bdd; + for (const auto& b : all_bdd) + { + if (needed_bdd.count(bdd_not(b))) + continue; + needed_bdd.insert(b); + } + + std::vector> sum_terms; + sum_terms.reserve(all_bdd.size()); + std::set needed_prods; + // Do sth smart here + std::vector sum_terms_pos; + std::vector sum_terms_neg; + std::vector intersect; + for (const auto& b : needed_bdd) + { + sum_terms_pos.clear(); + sum_terms_neg.clear(); + // Compute the ISOP of the primal and dual + // Use the repr that adds less terms - minato_isop cond(b); bdd prod; - while ((prod = cond.next()) != bddfalse) - { - prod_vars.clear(); - // Check if existing - auto it = bdd2var_.find(prod); - if (it != bdd2var_.end()) - plus_vars.push_back(it->second); - else - { - // Create - while (prod != bddfalse && prod != bddtrue) - { - unsigned v = - input_var(bddvar_to_num.at(bdd_var(prod))); - if (bdd_high(prod) == bddfalse) + minato_isop cond_isop(b); + while ((prod = cond_isop.next()) != bddfalse) + sum_terms_pos.push_back(prod); + + cond_isop = minato_isop(bdd_not(b)); + while ((prod = cond_isop.next()) != bddfalse) + sum_terms_neg.push_back(prod); + + std::sort(sum_terms_pos.begin(), sum_terms_pos.end(), + bdd_less_than()); + std::sort(sum_terms_neg.begin(), sum_terms_neg.end(), + bdd_less_than()); + + intersect.clear(); + std::set_intersection(needed_prods.cbegin(), needed_prods.end(), + sum_terms_pos.cbegin(), sum_terms_pos.cend(), + std::back_inserter(intersect), bdd_less_than()); + unsigned n_add_pos = 0; + std::for_each(sum_terms_pos.begin(), sum_terms_pos.end(), + [&n_add_pos, &intersect](const auto& b) { - v = aig_not(v); - prod = bdd_low(prod); - } - else - prod = bdd_high(prod); - prod_vars.push_back(v); + if (std::find(intersect.cbegin(), intersect.cend(), + b) == intersect.cend()) + n_add_pos += bdd_nodecount(b); + }); + + intersect.clear(); + std::set_intersection(needed_prods.cbegin(), needed_prods.end(), + sum_terms_neg.cbegin(), sum_terms_neg.cend(), + std::back_inserter(intersect), bdd_less_than()); + unsigned n_add_neg = 0; + std::for_each(sum_terms_neg.begin(), sum_terms_neg.end(), + [&n_add_neg, &intersect](const auto& b) + { + if (std::find(intersect.cbegin(), intersect.cend(), + b) == intersect.cend()) + n_add_neg += bdd_nodecount(b); + }); + + if (n_add_pos <= n_add_neg) + { + needed_prods.insert(sum_terms_pos.begin(), sum_terms_pos.end()); + sum_terms.emplace_back(std::move(sum_terms_pos)); + } + else + { + needed_prods.insert(sum_terms_neg.begin(), sum_terms_neg.end()); + sum_terms.emplace_back(std::move(sum_terms_neg)); + } + } + + // Now we need to compute the prod_terms + // todo switch to using id() to avoid ref count + // and use a map + std::vector> prod_terms; + prod_terms.reserve(needed_prods.size()); + for (bdd aprod : needed_prods) //apord : i1&ni2... + { + prod_terms.emplace_back(); + auto& ptv = prod_terms.back(); + + while (aprod != bddtrue) + { + bdd topvar = bdd_ithvar(bdd_var(aprod)); + bdd aprod_low = bdd_low(aprod); + if (aprod_low == bddfalse) + { + ptv.push_back(topvar); + aprod = bdd_high(aprod); + } + else + { + ptv.push_back(bdd_not(topvar)); + aprod = aprod_low; + } + } + std::sort(ptv.begin(), ptv.end(), + bdd_less_than()); + } + + // Now we need to count and then create the stack + // We start with the products + auto bdd_pair_hash = [](const auto& p) noexcept + { + return pair_hash()(std::make_pair( + (unsigned) p.first.id(), + (unsigned) p.second.id())); + }; + + std::unordered_map, unsigned, + decltype(bdd_pair_hash)> occur_map(prod_terms.size(), + bdd_pair_hash); + auto count_occ = [&occur_map](const auto& term) + { + unsigned l = term.size(); + for (unsigned i = 0; i < l; ++i) + for (unsigned j = i + 1; j < l; ++j) + { + auto [it, ins] = + occur_map.try_emplace({term[i], term[j]} , 0); + it->second += 1; + } + }; + auto uncount_occ = [&occur_map](const auto& term) + { + unsigned l = term.size(); + for (unsigned i = 0; i < l; ++i) + for (unsigned j = i + 1; j < l; ++j) + { + assert(occur_map.at({term[i], term[j]}) >= 1); + occur_map[{term[i], term[j]}] -= 1; + } + }; + for (const auto& pterm : prod_terms) + count_occ(pterm); + + auto and_ = [this](const auto& mi) + { + assert(bdd2var_.count(mi.first.first.id())); + assert(bdd2var_.count(mi.first.second.id())); + // Internal creation + aig_and(bdd2var_[mi.first.first.id()], bdd2var_[mi.first.second.id()]); + return mi.first.first & mi.first.second; + }; + + auto get_max = [&occur_map] + { + assert(occur_map.cbegin() != occur_map.cend()); + auto itm = + std::max_element(occur_map.cbegin(), occur_map.cend(), + [](const auto& it1, const auto& it2) + { return std::make_tuple(it1.second, + it1.first.first.id(), + it1.first.second.id()) + < std::make_tuple(it2.second, + it2.first.first.id(), + it2.first.second.id()); }); + if (itm == occur_map.cend()) + throw std::runtime_error("Empty occurence map!"); + return *itm; + }; + + while (!occur_map.empty()) + { + auto max_elem = get_max(); + unsigned n_occur_old = max_elem.second; + if (max_elem.second == 0) + break; + + // Create the gate + bdd andcond = and_(max_elem); + // Update + // Check in all prods if this exists and update + unsigned n_occur = 0; + + for (auto& pterm : prod_terms) + { + // todo, too costly right now + // Find left and right + // Note, left is always to the left of right + auto itl = std::find(pterm.begin(), pterm.end(), + max_elem.first.first); + auto itr = + itl == pterm.end() ? pterm.end() + : std::find(itl+1, pterm.end(), + max_elem.first.second); + + if ((itl != pterm.end()) && (itr != pterm.end())) + { + ++n_occur; + // uncount -> modifiy -> count + uncount_occ(pterm); + pterm.erase(itr); //Order matters + pterm.erase(itl); + pterm.push_back(andcond); + std::sort(pterm.begin(), pterm.end(), + bdd_less_than()); + count_occ(pterm); + } + } + assert(n_occur_old == n_occur); + } + // All products should now be created + assert(std::all_of(needed_prods.cbegin(), needed_prods.cend(), + [this](const bdd& aprod) + { return bdd2aigvar(aprod) > 0; })); + + // We have created all products, now we need the sums + // We basically do the same but with or + occur_map.clear(); + for (const auto& sterm : sum_terms) + // a & b = b & a only count once + count_occ(sterm); + + auto or_ = [this](const auto& mi) + { + assert(bdd2var_.count(mi.first.first.id())); + assert(bdd2var_.count(mi.first.second.id())); + // Internal creation + aig_or(bdd2var_[mi.first.first.id()], bdd2var_[mi.first.second.id()]); + return mi.first.first | mi.first.second; + }; + + while (!occur_map.empty()) + { + auto max_elem = get_max(); + unsigned n_occur_old = max_elem.second; + if (max_elem.second == 0) + break; + // Create the gate + bdd orcond = or_(max_elem); + // Update + // Check in all prods if this exists and update + unsigned n_occur = 0; + + for (auto& sterm : sum_terms) + { + // todo, too costly right now + // Find left and right + auto itl = std::find(sterm.begin(), sterm.end(), + max_elem.first.first); + auto itr = + itl == sterm.end() ? sterm.end() + : std::find(itl+1, sterm.end(), max_elem.first.second); + + if ((itl != sterm.end()) && (itr != sterm.end())) + { + ++n_occur; + uncount_occ(sterm); + sterm.erase(itr); //Order matters + sterm.erase(itl); + sterm.push_back(orcond); + std::sort(sterm.begin(), sterm.end(), + bdd_less_than()); + count_occ(sterm); + } + } + assert(n_occur_old == n_occur); + } + } + + aig_ptr + aig::parse_aag(const std::string& aig_file, + bdd_dict_ptr dict) + { + std::ifstream iss(aig_file, std::ios::in); + if (iss) + return parse_aag(iss, aig_file, dict); + else + throw std::runtime_error("Unable to open " + aig_file + '\n'); + } + + aig_ptr + aig::parse_aag(const char* data, + const std::string& filename, + bdd_dict_ptr dict) + { + std::string data_s(data); + std::istringstream iss(data_s); + return parse_aag(iss, filename, dict); + } + + aig_ptr + aig::parse_aag(std::istream& iss, + const std::string& filename, + bdd_dict_ptr dict) + { + //result + auto [in_names__, out_names__, next_latches__, outputs__, gates__] = + parse_aag_impl_(iss, filename); + + aig_ptr res_ptr = + std::make_shared(in_names__, out_names__, + next_latches__.size(), dict); + aig& circ = *res_ptr; + res_ptr->max_var_ = + (in_names__.size() + next_latches__.size() + gates__.size())*2; + std::swap(res_ptr->next_latches_, next_latches__); + std::swap(res_ptr->outputs_, outputs__); + std::swap(res_ptr->and_gates_, gates__); + + // Create all the bdds/vars + // true/false/latches/inputs already exist + // Get the gatenumber corresponding to an output + auto v2g = [&](unsigned v)->unsigned + { + v = circ.aig_pos(v); + v /= 2; + assert(v >= 1 + circ.num_inputs_ + circ.num_latches_ + && "Variable does not correspond to a gate"); + return v - (1 + circ.num_inputs_ + circ.num_latches_); + }; + auto& var2bdd = circ.var2bdd_; + auto& bdd2var = circ.bdd2var_; + std::function get_gate_bdd; + get_gate_bdd = [&](unsigned g)->bdd + { + assert(v2g(circ.gate_var(g) == g)); + + unsigned v = circ.gate_var(g); + auto it = var2bdd.find(v); + if (it != var2bdd.end()) + { + assert(bdd2var.at(var2bdd.at(v).id()) == v + && "Inconsistent bdd!\n"); + return it->second; + } + //get the vars of the input to the gates + bdd gsbdd[2]; + unsigned gsv[2] = {circ.and_gates_.at(g).first, + circ.and_gates_.at(g).second}; + // Check if the exist + for (unsigned i : {0, 1}) + { + it = var2bdd.find(gsv[i]); + if (it != var2bdd.end()) + gsbdd[i] = it->second; + else + { + // Construct it + gsbdd[i] = get_gate_bdd(v2g(circ.aig_pos(gsv[i]))); + // Odd idx -> negate + if (gsv[i]&1) + gsbdd[i] = bdd_not(gsbdd[i]); + } + } + bdd gbdd = bdd_and(gsbdd[0], gsbdd[1]); + circ.register_new_lit_(v, gbdd); + return gbdd; + }; + // Do this for each gate then everything should exist + // Also it should be consistent + const unsigned n_gates = res_ptr->num_gates(); + for (unsigned g = 0; g < n_gates; ++g) + get_gate_bdd(g); + //Check that all outputs and next_latches exist + auto check = [&var2bdd](unsigned v) + { + if (not (var2bdd.count(v))) + throw std::runtime_error("variable " + std::to_string(v) + + " has no bdd associated!\n"); + }; + std::for_each(circ.next_latches_.begin(), circ.next_latches_.end(), + check); + std::for_each(circ.outputs_.begin(), circ.outputs_.end(), + check); + return res_ptr; + } + + twa_graph_ptr aig::as_automaton(bool keepsplit) const + { + auto aut = make_twa_graph(dict_); + + assert(num_latches_ < sizeof(unsigned)*CHAR_BIT); + + const unsigned n_max_states = 1 << num_latches_; + aut->new_states(n_max_states); + + auto s2bdd = [&](unsigned s) + { + bdd b = bddtrue; + for (unsigned j = 0; j < num_latches_; ++j) + { + // Get the j-th latch in this partial strategy + // If high -> not negated + b &= latch_bdd(j, !(s & 1)); + s >>= 1; + } + return b; + }; + + std::vector outbddvec; + for (auto& ao : output_names_) + outbddvec.push_back(bdd_ithvar(aut->register_ap(ao))); + // Also register the ins + for (auto& ai : input_names_) + aut->register_ap(ai); + + std::vector outcondbddvec; + for (auto ov : outputs_) + outcondbddvec.push_back(aigvar2bdd(ov)); + + auto get_out = [&](const bdd& sbdd, const bdd& insbdd) + { + bdd out = bddtrue; + for (unsigned i = 0; i < num_outputs_; ++i) + { + if ((outcondbddvec[i] & sbdd & insbdd) != bddfalse) + out &= outbddvec[i]; + else + out -= outbddvec[i]; + } + return out; + }; + + + //Nextlatch is a function of latch and input + std::vector nxtlbddvec(num_latches_); + for (unsigned i = 0; i < num_latches_; ++i) + nxtlbddvec[i] = aigvar2bdd(next_latches_[i]); + + auto get_dst = [&](const bdd& sbdd, const bdd& insbdd) + { + // the first latch corresponds to the most significant digit + unsigned dst = 0; + unsigned off = 1; + for (unsigned i = 0; i < num_latches_; ++i) + { + bdd ilatch = nxtlbddvec[i]; + // evaluate + ilatch = (ilatch & sbdd & insbdd); + dst += (ilatch != bddfalse)*off; + off *= 2; + } + return dst; + }; + + bdd alli = bddtrue; + std::vector ibddvec(num_inputs_); + for (unsigned i = 0; i < num_inputs_; ++i) + { + ibddvec[i] = input_bdd(i); + alli &= ibddvec[i]; + } + + std::deque todo; + todo.push_back(0); + std::vector seen(n_max_states, false); + seen[0] = true; + + std::unordered_map splayer_map; + //dst + cond -> state + auto get_id = [](const bdd& ocond, unsigned dst) + { + constexpr unsigned shift = (sizeof(size_t) / 2) * 8; + size_t u = dst; + u <<= shift; + u += (unsigned) ocond.id(); + return u; + }; + + while (!todo.empty()) + { + unsigned s = todo.front(); + todo.pop_front(); + + // bdd of source state + bdd srcbdd = s2bdd(s); + // All possible inputs + // Note that for unspecified input sequences the + // result is unspecified as well + + //todo change to new format + for (auto inbdd : minterms_of(bddtrue, alli)) + { + // Get the target state + unsigned sprime = get_dst(srcbdd, inbdd); + // Get the associated cout cond + bdd outbdd = get_out(srcbdd, inbdd); + + if (keepsplit) + { + auto id = get_id(outbdd, sprime); + auto it = splayer_map.find(id); + if (it == splayer_map.end()) + { + unsigned ntarg = aut->new_state(); + splayer_map[id] = ntarg; + aut->new_edge(s, ntarg, inbdd); + aut->new_edge(ntarg, sprime, outbdd); } - plus_vars.push_back(aig_and(prod_vars)); + else + aut->new_edge(s, it->second, inbdd); + } + else + aut->new_edge(s, sprime, inbdd & outbdd); + if (!seen[sprime]) + { + seen[sprime] = true; + todo.push_back(sprime); + } + } + } + aut->purge_unreachable_states(); + aut->merge_edges(); + if (keepsplit) + // Mealy machines by definition start with env trans + alternate_players(aut, false, false); + return aut; + } + + void aig::circ_init() + { + state_.resize(max_var_ + 2); + std::fill(state_.begin(), state_.end(), false); + // Set "true" + state_[1] = 1; + } + + void aig::circ_step(const std::vector& inputs) + { + assert(inputs.size() == num_inputs() + && "Input length does not match"); + assert(state_.size() == max_var_ + 2 + && "State vector does not have the correct size.\n" + "Forgot to initialize?"); + // Set the inputs + for (unsigned i = 0; i < num_inputs(); ++i) + { + state_[input_var(i)] = inputs[i]; + state_[input_var(i, true)] = !inputs[i]; + } + // Latches already have correct state either from + // init or from last iteration + + // Loop through all gates + const unsigned ng = num_gates(); + for (unsigned i = 0; i < ng; ++i) + { + unsigned var_g = gate_var(i); + state_[var_g] = state_[and_gates_[i].first] + & state_[and_gates_[i].second]; + state_[aig_not(var_g)] = !state_[var_g]; + } + // Update latches + const auto& nl = next_latches(); + for (unsigned i = 0; i < num_latches(); ++i) + { + unsigned lv = latch_var(i); + state_[lv] = state_[nl[i]]; + state_[aig_not(lv)] = !state_[lv]; + } + + } +} + +namespace +{ + using namespace spot; + + // We have to decide which actual output to use: + // Heuristic : Use the assignment having the least highs + static std::vector> + choose_outc(const std::vector>& + strat_vec, + const bdd& all_inputs) + { + std::vector> used_outc; + + for (auto&& astrat : strat_vec) + { + used_outc.emplace_back(astrat.first->num_edges()+1); + auto& this_outc = used_outc.back(); + + for (auto&& e: astrat.first->edges()) + { + assert(e.cond != bddfalse); + bdd bout = bdd_exist(e.cond, all_inputs); + assert(((bout & bdd_existcomp(e.cond, all_inputs)) == e.cond) && + "Precondition (in) & (out) == cond violated"); + // low is good, dc is ok, high is bad + this_outc[astrat.first->edge_number(e)] = + bdd_satoneshortest(bout, 0, 1, 5); + } + } + //Done + return used_outc; + } + + static void + state_to_vec(std::vector& v, unsigned s, + unsigned offset) + { + v.clear(); + unsigned i = offset; + while (s > 0) + { + if (s & 1) + v.push_back(i); + s >>= 1; + ++i; + } + } + + static void + output_to_vec(std::vector& v, + std::map& out_dc_vec, bdd b, + const std::unordered_map& + bddvar_to_outputnum) + { + // We do not care about an output if it does not appear in the bdd + for (auto& [_, dc_v] : out_dc_vec) + dc_v = true; + v.clear(); + while (b != bddtrue) + { + unsigned i = bddvar_to_outputnum.at(bdd_var(b)); + out_dc_vec.at(i) = false; + assert((bdd_low(b) == bddfalse) || (bdd_high(b) == bddfalse)); + if (bdd_low(b) == bddfalse) + { + v.push_back(i); + b = bdd_high(b); + } + else + b = bdd_low(b); + } + } + + // Transforms a vector of strategies and their respective + // outputs into an Aig + static aig_ptr + auts_to_aiger(const std::vector>& + strat_vec, + const char* mode) + { + // The aiger circuit cannot encode the acceptance condition + // Test that the acceptance condition is true + for (auto&& astrat : strat_vec) + if (!astrat.first->acc().is_t()) + { + std::cerr << "Acc cond must be true not " << astrat.first->acc() + << std::endl; + throw std::runtime_error("Cannot turn automaton into " + "aiger circuit"); + } + + // get the propositions + std::vector input_names; + std::vector output_names; + bdd all_inputs = bddtrue; + bdd all_outputs = bddtrue; + + // Join all the outputs + for (auto& astrat : strat_vec) + all_outputs &= astrat.second; + + std::vector all_inputs_vec; + std::unordered_map bddvar_to_num; + { + unsigned i_in = 0; + unsigned i_out = 0; + for (auto& astrat : strat_vec) + { + for (const auto& ap : astrat.first->ap()) + { + int bddvar = + astrat.first->get_dict()-> + has_registered_proposition(ap, astrat.first); + assert(bddvar >= 0); + bdd b = bdd_ithvar(bddvar); + if (bdd_implies(all_outputs, b)) // ap is an output AP + { + output_names.push_back(ap.ap_name()); + auto [it, inserted] = bddvar_to_num.try_emplace(bddvar, + i_out++); + if (SPOT_UNLIKELY(!inserted)) + throw std::runtime_error("Intersecting outputs"); + } + else // ap is an input AP -> check if already registered + { + if (bdd_implies(all_inputs, b)) + continue; + // New input + input_names.push_back(ap.ap_name()); + all_inputs &= b; + bddvar_to_num[bddvar] = i_in++; + } + } + } + } + + // Decide on which outcond to use + // The edges of the automaton all have the form in&out + // due to the unsplit + // however we need the edge out cond to be encoded by the aiger + // so we have to decide which minterm to use + + std::vector> used_outc; + // Heuristic: Use the assignment with the shortest path + // according to a weight function depending on the number + // of highs, lows and do-not-cares + used_outc = choose_outc(strat_vec, all_inputs); + + // Encode state in log2(num_states) latches. + // The latches of each strategy have to be separated + // as the strategies advance synchronously + // so we get latches = [latches_0, latches_1, ....] + + // latches per strat + // If the states in the automaton are named, + // it is assumed that they are named by integers + // and these values will be used for encoding + // This coding has to ensure that the initial state + // is zero + // attention : least significant bit -> left / idx 0 + std::vector> state_numbers; + std::vector log2n; + log2n.reserve(strat_vec.size()); + // cumulative sum of latches across strats + std::vector latch_offset; + latch_offset.reserve(strat_vec.size()+1); + unsigned n_latches = 0; + for (const auto& astrat : strat_vec) + { + state_numbers.emplace_back(); + state_numbers.back().reserve(astrat.first->num_states()); + unsigned max_index = 0; + // Check if named + if (const auto* s_names = + astrat.first-> + get_named_prop>("state-names")) + { + std::transform(s_names->cbegin(), s_names->cend(), + std::back_inserter(state_numbers.back()), + [&max_index](const auto& sn) + { + unsigned su = std::stoul(sn); + max_index = std::max(max_index, su); + return su; + }); + ++max_index; + } + else + { + max_index = astrat.first->num_states(); + state_numbers.back().resize(astrat.first->num_states()); + std::iota(state_numbers.back().begin(), + state_numbers.back().end(), 0); + // Ensure 0 <-> init state + std::swap(state_numbers.back()[0], + state_numbers.back()[astrat.first-> + get_init_state_number()]); + } + // Largest index to encode -> num_states()-1 + log2n.push_back(std::ceil(std::log2(max_index))); + latch_offset.push_back(n_latches); + n_latches += log2n.back(); + } + latch_offset.push_back(n_latches); + + assert(output_names.size() == (unsigned) bdd_nodecount(all_outputs)); + aig_ptr circuit_ptr = + std::make_shared(input_names, output_names, + n_latches, strat_vec[0].first->get_dict()); + aig& circuit = *circuit_ptr; + + // Latches and outputs are expressed as a bdd + // The bdd are then translated into aiger circuits + // relying on different strategies + const unsigned n_outs = output_names.size(); + std::vector latch(n_latches, bddfalse); + std::vector out(n_outs, bddfalse); + std::vector out_dc(n_outs, bddfalse); + + std::vector out_vec; + out_vec.reserve(n_outs); + std::map out_dc_vec; //Bdd where out can be high + + std::vector next_state_vec; + next_state_vec.reserve(n_latches); + + // Loop over the different strategies + for (unsigned i = 0; i < strat_vec.size(); ++i) + { + auto&& [astrat, aouts] = strat_vec[i]; + const auto& sn = state_numbers.at(i); + + auto latchoff = latch_offset[i]; + auto latchoff_next = latch_offset.at(i+1); + + auto alog2n = log2n[i]; + auto state2bdd = [&](auto s) + { + auto s2 = sn[s]; + bdd b = bddtrue; + for (unsigned j = 0; j < alog2n; ++j) + { + // Get the j-th latch in this partial strategy + // If high -> not negated + b &= circuit.latch_bdd(latchoff + j, !(s2 & 1)); + s2 >>= 1; + } + assert(s2 <= 1); + return b; + }; + + //set the possible do not cares for this strat + { + out_dc_vec.clear(); + bdd r_outs = aouts; + while (r_outs != bddtrue) + { + out_dc_vec[bddvar_to_num.at(bdd_var(r_outs))] = false; + r_outs = bdd_high(r_outs); + } + } + + for (unsigned s = 0; s < astrat->num_states(); ++s) + { + // Convert src state to bdd + bdd src_bdd = state2bdd(s); + + for (const auto& e : astrat->out(s)) + { + // High latches of dst + state_to_vec(next_state_vec, sn[e.dst], latchoff); + + // Get high outs depending on cond + output_to_vec(out_vec, out_dc_vec, + used_outc[i][astrat->edge_number(e)], + bddvar_to_num); + + // The condition that joins in_cond and src + // Note that the circuit and the strategy share a + // bdd_dict + bdd tot_cond = src_bdd & bdd_exist(e.cond, aouts); + // Test should not have any outs from other strats + + // Set in latches/outs having "high" + for (auto&& nl : next_state_vec) + { + assert (latchoff <= nl && nl < latchoff_next); + latch.at(nl) |= tot_cond; + } + for (auto&& ao : out_vec) + out.at(ao) |= tot_cond; + // And the do not cares + for (const auto& [ao, v] : out_dc_vec) + if (v) + out_dc.at(ao) |= tot_cond; + } // edges + } // state + } //strat + + struct tr_opt + { + char method; + bool use_dual = false; + bool use_dontcare = false; + int use_split_off = 0; + }; + + auto to_treat = [&mode]() + { + std::vector res; + std::stringstream s; + s << mode; + std::string buffer; + std::string buffer2; + + while (std::getline(s, buffer, ',')) + { + tr_opt this_opt; + std::stringstream s2; + s2 << buffer; + std::getline(s2, buffer2, '+'); + // Method + if (buffer2 == "ite") + this_opt.method = 0; + else if (buffer2 == "isop") + this_opt.method = 1; + else if (buffer2 == "both") + this_opt.method = 2; + else if (buffer2 == "optim") + this_opt.method = 3; + else + throw std::runtime_error("Encoding option unrecognised, " + "expected ite, isop or both."); + + if (s2) + while (std::getline(s2, buffer2, '+')) + { + if (buffer2 == "ud") + this_opt.use_dual = true; + else if (buffer2 == "dc") + this_opt.use_dontcare = true; + else if (buffer2.find("sub") == 0) + { + if (buffer2.size() != 4) + { + std::cerr << "Got option " << mode << '\n'; + throw std::runtime_error("Option for splitting off" + " sub-expressions is " + "expected to have " + "4 chars"); + } + this_opt.use_split_off = + (int)buffer2[3] - 48; + if ((this_opt.use_split_off < 0) + || (this_opt.use_split_off > 2)) + throw std::runtime_error("Option for splitting off " + "must be one of sub0, sub1, " + "or sub2"); + } + else + throw std::runtime_error(buffer + " does not describe a " + "mode supported for AIGER creation. Expected\n" + "ite|isop|both[+sub][+dc][+ud]\n" + "or a coma separated list of such expressions."); + } + res.push_back(std::move(this_opt)); + } + return res; + }(); + + auto sf = circuit.get_safe_point_(); + unsigned min_gates = -1u; + aig::safe_stash ss; + std::function bdd2var; + std::function bdd2var_min; + + // Fuse the do not cares + for (unsigned i = 0; i < n_outs; ++i) + out_dc[i] |= out[i]; + + for (const auto& amodedescr : to_treat) + { + if (amodedescr.method == 3) + { + // Here it is more tricky + // First get a vector with all conditions needed in the + // strategy + std::vector all_cond; + all_cond.reserve(out.size() + latch.size()); + all_cond.insert(all_cond.end(), out.cbegin(), out.cend()); + all_cond.insert(all_cond.end(), latch.cbegin(), latch.cend()); + // Then construct it + circuit.encode_all_bdds(all_cond); + bdd2var = [&circuit](const bdd& b, const bdd&)->unsigned + {return circuit.bdd2aigvar(b); }; + } + else + { + bdd2var = [&circuit, amodedescr](const auto& b1, const auto& b2) + { + static std::vector alt_conds; + alt_conds.clear(); + + alt_conds.push_back(b1); + + if (amodedescr.use_dontcare && (b2 != bddfalse)) + { + assert(bdd_implies(b1, b2)); + alt_conds.push_back(b2); + } + + return circuit.encode_bdd(alt_conds, amodedescr.method, + amodedescr.use_dual, + amodedescr.use_split_off); + }; + + // Create the vars + std::vector alt_conds(amodedescr.use_dontcare ? 1 : 2); + for (unsigned i = 0; i < n_outs; ++i) + { + if (circuit.num_gates() > min_gates) + break; + circuit.set_output(i, bdd2var(out[i], out_dc[i])); + } + for (unsigned i = 0; i < n_latches; ++i) + { + if (circuit.num_gates() > min_gates) + break; + circuit.set_next_latch(i, bdd2var(latch[i], bddfalse)); } } - // Done building - return aig_or(plus_vars); - } - - // Takes a bdd, computes the corresponding literal - // using its INF - unsigned bdd2INFvar(bdd b) - { - // F = !v&low | v&high - // De-morgan - // !(!v&low | v&high) = !(!v&low) & !(v&high) - // !v&low | v&high = !(!(!v&low) & !(v&high)) - auto b_it = bdd2var_.find(b); - if (b_it != bdd2var_.end()) - return b_it->second; - - unsigned v_var = bdd2var_.at(bdd_ithvar(bdd_var(b))); - - bdd b_branch[2] = {bdd_low(b), bdd_high(b)}; - unsigned b_branch_var[2]; - - for (unsigned i: {0, 1}) + // Overwrite the stash if we generated less gates + if (circuit.num_gates() < min_gates) { - auto b_branch_it = bdd2var_.find(b_branch[i]); - if (b_branch_it == bdd2var_.end()) - b_branch_var[i] = bdd2INFvar(b_branch[i]); - else - b_branch_var[i] = b_branch_it->second; + min_gates = circuit.num_gates(); + ss = circuit.roll_back_(sf, true); + bdd2var_min = bdd2var; } - - unsigned r = aig_not(aig_and(v_var, b_branch_var[1])); - unsigned l = aig_not(aig_and(aig_not(v_var), b_branch_var[0])); - return aig_not(aig_and(l, r)); + else + circuit.roll_back_(sf, false); } + //Use the best sol + circuit.reapply_(sf, ss); + // Reset them + for (unsigned i = 0; i < n_outs; ++i) + circuit.set_output(i, bdd2var_min(out[i], out_dc[i])); + for (unsigned i = 0; i < n_latches; ++i) + circuit.set_next_latch(i, bdd2var_min(latch[i], bddfalse)); + return circuit_ptr; + } // auts_to_aiger +} - void - print(std::ostream& os) const +namespace spot +{ + + aig_ptr + strategy_to_aig(const const_twa_graph_ptr& aut, const char* mode) + { + if (!aut) + throw std::runtime_error("aut cannot be null"); + + return auts_to_aiger({{aut, get_synthesis_outputs(aut)}}, mode); + } + + aig_ptr + strategies_to_aig(const std::vector& strat_vec, + const char *mode) + { + std::for_each(strat_vec.begin()+1, strat_vec.end(), + [usedbdd = strat_vec.at(0)->get_dict()](const auto& s) + { + if (usedbdd != s->get_dict()) + throw std::runtime_error("All strategies have to " + "share a bdd_dict!\n"); + }); + + std::vector> new_vec; + new_vec.reserve(strat_vec.size()); + + bdd all_outputs = bddtrue; + for (auto& astrat : strat_vec) { - // Writing gates to formatted buffer speed-ups output - // as it avoids "<<" calls - // vars are unsigned -> 10 digits at most - char gate_buffer[3*10+5]; - auto write_gate = [&](unsigned o, unsigned i0, unsigned i1) - { - std::sprintf(gate_buffer, "%u %u %u\n", o, i0, i1); - os << gate_buffer; - }; - // Count active gates - unsigned n_gates=0; - for (auto& g : and_gates_) - if ((g.first != 0) && (g.second != 0)) - ++n_gates; - // Note max_var_ is now an upper bound - os << "aag " << max_var_ / 2 - << ' ' << num_inputs_ - << ' ' << num_latches_ - << ' ' << num_outputs_ - << ' ' << n_gates << '\n'; - for (unsigned i = 0; i < num_inputs_; ++i) - os << (1 + i) * 2 << '\n'; - for (unsigned i = 0; i < num_latches_; ++i) - os << (1 + num_inputs_ + i) * 2 << ' ' << latches_[i] << '\n'; - for (unsigned i = 0; i < outputs_.size(); ++i) - os << outputs_[i] << '\n'; - for (unsigned i=0; i& ins, + const std::vector& outs) + { + if (!aut) + throw std::runtime_error("aut cannot be null"); + + // Make sure ins and outs are disjoint + { + std::vector all_ap = ins; + all_ap.insert(all_ap.end(), outs.begin(), outs.end()); + check_double_names(all_ap, "Atomic propositions appears in input " + "and output propositions; "); + } + // Register all to make sure they exist in the aut + std::for_each(ins.begin(), ins.end(), + [s = aut](auto&& e){s->register_ap(e); }); + bdd all_outputs = bddtrue; + std::for_each(outs.begin(), outs.end(), + [&ao = all_outputs, s=aut](auto&& e) + {ao &= bdd_ithvar(s->register_ap(e)); }); + // todo Some additional checks? + return auts_to_aiger({{aut, all_outputs}}, mode); + } + + // Note: This ignores the named property + aig_ptr + strategies_to_aig(const std::vector& strat_vec, + const char *mode, + const std::vector& ins, + const std::vector>& outs) + { + if (strat_vec.size() != outs.size()) + throw std::runtime_error("Expected as many outs as strategies!\n"); + + std::for_each(strat_vec.begin()+1, strat_vec.end(), + [usedbdd = strat_vec.at(0)->get_dict()](auto&& it) + { + if (usedbdd != it->get_dict()) + throw std::runtime_error("All strategies have to " + "share a bdd_dict!\n"); + }); + + { + std::vector all_ap; + for (const auto& av : outs) + all_ap.insert(all_ap.end(), av.begin(), av.end()); + check_double_names(all_ap, "output proposition appears in " + "multiple strategies: "); + all_ap.insert(all_ap.end(), ins.begin(), ins.end()); + check_double_names(all_ap, "Atomic propositions appears in input " + "and output propositions: "); + } + + std::vector> new_vec; + new_vec.reserve(strat_vec.size()); + + for (size_t i = 0; i < strat_vec.size(); ++i) + { + // Register all to make sure they exist in the aut + std::for_each(ins.begin(), ins.end(), + [s=strat_vec[i]](auto&& e){s->register_ap(e); }); + bdd this_outputs = bddtrue; + std::for_each(outs[i].begin(), outs[i].end(), + [&to = this_outputs, s=strat_vec[i]](auto&& e) + {to &= bdd_ithvar(s->register_ap(e)); }); + if (this_outputs == bddfalse) + throw std::runtime_error("Inconsistency in outputs of strat " + + std::to_string(i) + ".\n"); + // todo Some additional checks? + new_vec.emplace_back(strat_vec[i], this_outputs); + } + return auts_to_aiger(new_vec, mode); + } + + std::ostream & + print_aiger(std::ostream &os, const_aig_ptr circuit) + { + if (not circuit) + return os; //Print nothing in case of nullptr + + auto n_inputs = circuit->num_inputs(); + auto n_outputs = circuit->num_outputs(); + auto n_latches = circuit->num_latches(); + auto gates = circuit->gates(); + + // Writing gates to formatted buffer speed-ups output + // as it avoids "<<" calls + // vars are unsigned -> 10 digits at most + char gate_buffer[3 * 10 + 5]; + auto write_gate = [&](unsigned o, unsigned i0, unsigned i1) { + std::sprintf(gate_buffer, "%u %u %u\n", o, i0, i1); + os << gate_buffer; }; - - static void - state_to_vec(std::vector& v, unsigned s) + // Count active gates + unsigned n_gates = 0; + for (auto &g : gates) + if ((g.first != 0) && (g.second != 0)) + ++n_gates; + // Note max_var_ is now an upper bound + os << "aag " << circuit->max_var() / 2 + << ' ' << n_inputs + << ' ' << n_latches + << ' ' << n_outputs + << ' ' << n_gates << '\n'; + for (unsigned i = 0; i < n_inputs; ++i) + os << (1 + i) * 2 << '\n'; + for (unsigned i = 0; i < n_latches; ++i) + os << (1 + n_inputs + i) * 2 + << ' ' << circuit->next_latches()[i] << '\n'; + for (unsigned i = 0; i < n_outputs; ++i) + os << circuit->outputs()[i] << '\n'; + for (unsigned i = 0; i < n_gates; ++i) + if ((gates[i].first != 0) + && (gates[i].second != 0)) + write_gate(circuit->gate_var(i), + gates[i].first, + gates[i].second); + for (unsigned i = 0; i < n_inputs; ++i) + os << 'i' << i << ' ' << circuit->input_names()[i] << '\n'; + if (n_outputs > 0) { - for (unsigned i = 0; i < v.size(); ++i) - { - v[i] = s & 1; - s >>= 1; - }; + unsigned i; + for (i = 0; i < n_outputs - 1; ++i) + os << 'o' << i << ' ' << circuit->output_names()[i] << '\n'; + os << 'o' << i << ' ' << circuit->output_names()[i]; } - - static void - output_to_vec(std::vector& v, bdd b, - const std::unordered_map& - bddvar_to_outputnum) - { - std::fill(v.begin(), v.end(), false); - while (b != bddtrue && b != bddfalse) - { - unsigned i = bddvar_to_outputnum.at(bdd_var(b)); - v.at(i) = (bdd_low(b) == bddfalse); - if (v[i]) - b = bdd_high(b); - else - b = bdd_low(b); - } - } - - static bdd - state_to_bdd(unsigned s, bdd all_latches) - { - bdd b = bddtrue; - unsigned size = bdd_nodecount(all_latches); - if (size) - { - unsigned st0 = bdd_var(all_latches); - for (unsigned i = 0; i < size; ++i) - { - b &= (s & 1) ? bdd_ithvar(st0 + i) : bdd_nithvar(st0 + i); - s >>= 1; - } - } - return b; - } - - // Switch initial state and 0 in the AIGER encoding, so that the - // 0-initialized latches correspond to the initial state. - static unsigned - encode_init_0(unsigned src, unsigned init) - { - return src == init ? 0 : src == 0 ? init : src; - } - - // Takes a product and returns the - // number of highs - inline unsigned count_high(bdd b) - { - unsigned high=0; - while (b != bddtrue) - { - if (bdd_low(b) == bddfalse) - { - ++high; - b = bdd_high(b); - } - else - { - assert(bdd_high(b) == bddfalse); - b = bdd_low(b); - } - } - return high; - } - - // Heuristic to minimize the number of gates - // in the resulting aiger - // the idea is to take the (valid) output with the - // least "highs" for each transition. - // Another idea is to chose conditions such that transitions - // can share output conditions. Problem this is a combinatorial - // problem and suboptimal solutions that can be computed in - // reasonable time have proven to be not as good - // Stores the outcondition to use in the used_outc vector - // for each transition in aut - std::vector maxlow_outc(const const_twa_graph_ptr& aut, - const bdd& all_inputs) - { - std::vector used_outc(aut->num_edges()+1, bddfalse); - - for (const auto &e : aut->edges()) - { - unsigned idx = aut->edge_number(e); - assert(e.cond != bddfalse); - bdd bout = bdd_exist(e.cond, all_inputs); - assert(((bout & bdd_existcomp(e.cond, all_inputs)) == e.cond) && - "Precondition (in) & (out) == cond violated"); - unsigned n_high=-1u; - while (bout != bddfalse) - { - bdd nextsat = bdd_satone(bout); - bout -= nextsat; - unsigned next_high = count_high(nextsat); - if (next_highacc().is_t()) - throw std::runtime_error("Cannot turn automaton into aiger circuit"); - - // get the propositions - std::vector input_names; - std::vector output_names; - bdd all_inputs = bddtrue; - std::vector all_inputs_vec; - std::unordered_map bddvar_to_num; - for (const auto& ap : aut->ap()) - { - int bddvar = aut->get_dict()->has_registered_proposition(ap, aut); - assert(bddvar >= 0); - bdd b = bdd_ithvar(bddvar); - if (bdd_implies(all_outputs, b)) // ap is an output AP - { - bddvar_to_num[bddvar] = output_names.size(); - output_names.emplace_back(ap.ap_name()); - } - else // ap is an input AP - { - bddvar_to_num[bddvar] = input_names.size(); - input_names.emplace_back(ap.ap_name()); - all_inputs &= b; - all_inputs_vec.push_back(b); - } - } - - // Decide on which outcond to use - // The edges of the automaton all have the form in&out - // due to the unsplit - // however we need the edge to be deterministic in out too - // So we need determinism and we also want the resulting aiger - // to have as few gates as possible - std::vector used_outc = maxlow_outc(aut, all_inputs); - - // Encode state in log2(num_states) latches. - unsigned log2n = std::ceil(std::log2(aut->num_states())); - unsigned st0 = aut->get_dict()->register_anonymous_variables(log2n, aut); - - unsigned num_outputs = output_names.size(); - unsigned init = aut->get_init_state_number(); - assert(num_outputs == (unsigned) bdd_nodecount(all_outputs)); - aig circuit(input_names, output_names, log2n); - - // Register - // latches - for (unsigned i = 0; i < log2n; ++i) - circuit.register_new_lit(circuit.latch_var(i), bdd_ithvar(st0+i)); - // inputs - for (unsigned i = 0; i < all_inputs_vec.size(); ++i) - circuit.register_new_lit(circuit.input_var(i), all_inputs_vec[i]); - // Latches and outputs are expressed as a DNF in which each term - // represents a transition. - // latch[i] (resp. out[i]) represents the i-th latch (resp. output) DNF. - - std::vector out_vec(output_names.size()); - std::vector next_state_vec(log2n); - if (strcasecmp(mode, "ISOP") == 0) - { - std::vector> latch(log2n); - std::vector> out(num_outputs); - // Keep track of bdd that were already transformed into a gate - std::unordered_map incond_map; - std::vector prod_state(log2n); - for (unsigned s = 0; s < aut->num_states(); ++s) - { - unsigned src = encode_init_0(s, init); - prod_state.clear(); - unsigned src2 = src; - for (unsigned i = 0; i < log2n; ++i) - { - unsigned v = circuit.latch_var(i); - prod_state.push_back(src2 & 1 ? v : circuit.aig_not(v)); - src2 >>= 1; - } - assert(src2 <= 1); - unsigned state_var = circuit.aig_and(prod_state); - // Done state var - - for (auto &e: aut->out(s)) - { - unsigned e_idx = aut->edge_number(e); - // Same outcond for all ins - const bdd &letter_out = used_outc[e_idx]; - output_to_vec(out_vec, letter_out, bddvar_to_num); - - unsigned dst = encode_init_0(e.dst, init); - state_to_vec(next_state_vec, dst); - - // Get the isops over the input condition - // Each isop only contains variables from in - // -> directly compute the corresponding - // variable and and-gate - bdd incond = bdd_exist(e.cond, all_outputs); - auto incond_var_it = incond_map.find(incond); - if (incond_var_it == incond_map.end()) - // The incond and its isops have not yet been calculated - { - bool inserted; - unsigned var = circuit.bdd2DNFvar(incond, bddvar_to_num); - std::tie(incond_var_it, inserted) = - incond_map.insert(std::make_pair(incond, var)); - assert(inserted && incond_var_it->second == var); - } - - // AND with state - unsigned t = - circuit.aig_and(state_var, incond_var_it->second); - // Set in latches/outs having "high" - for (unsigned i = 0; i < log2n; ++i) - if (next_state_vec[i]) - latch[i].push_back(t); - for (unsigned i = 0; i < num_outputs; ++i) - if (out_vec[i]) - out[i].push_back(t); - } // edge - } // state - - for (unsigned i = 0; i < log2n; ++i) - circuit.set_latch(i, circuit.aig_or(latch[i])); - for (unsigned i = 0; i < num_outputs; ++i) - circuit.set_output(i, circuit.aig_or(out[i])); - circuit.remove_unused(); - } - else if (strcasecmp(mode, "ITE") == 0) - { - std::vector latch(log2n, bddfalse); - std::vector out(num_outputs, bddfalse); - bdd all_latches = bddtrue; - for (unsigned i = 0; i < log2n; ++i) - all_latches &= bdd_ithvar(st0 + i); - - for (unsigned s = 0; s < aut->num_states(); ++s) - { - // Convert state to bdd - unsigned src = encode_init_0(s, init); - bdd src_bdd = state_to_bdd(src, all_latches); - - for (const auto& e : aut->out(src)) - { - unsigned dst = encode_init_0(e.dst, init); - state_to_vec(next_state_vec, dst); - // edges have the form - // f(ins) & f(outs) - // one specific truth assignment has been selected above - // and stored in used_outc - output_to_vec(out_vec, used_outc[aut->edge_number(e)], - bddvar_to_num); - // The condition that joins in_cond and src - bdd tot_cond = src_bdd & bdd_exist(e.cond, all_outputs); - - // Add to existing cond - for (unsigned i = 0; i < log2n; ++i) - if (next_state_vec[i]) - latch[i] |= tot_cond; - for (unsigned i = 0; i < num_outputs; ++i) - if (out_vec[i]) - out[i] |= tot_cond; - } // e - } // src - // Create the vars - for (unsigned i = 0; i < num_outputs; ++i) - circuit.set_output(i, circuit.bdd2INFvar(out[i])); - for (unsigned i = 0; i < log2n; ++i) - circuit.set_latch(i, circuit.bdd2INFvar(latch[i])); - } - else - { - throw std::runtime_error - ("print_aiger(): mode must be \"ISOP\" or \"ITE\""); - } - - return circuit; - } // aut_to_aiger_isop + return os; } std::ostream& - print_aiger(std::ostream& os, const const_twa_ptr& aut, const char* mode) + print_aiger(std::ostream& os, const const_twa_graph_ptr& aut, + const char* mode) { - auto a = down_cast(aut); - if (!a) - throw std::runtime_error("aiger output is only for twa_graph"); - - bdd* all_outputs = aut->get_named_prop("synthesis-outputs"); - - aig circuit = - aut_to_aiger(a, all_outputs ? *all_outputs : bdd(bddfalse), mode); - circuit.print(os); + print_aiger(os, strategy_to_aig(aut, mode)); return os; } } diff --git a/spot/twaalgos/aiger.hh b/spot/twaalgos/aiger.hh index 9c7270cbb..876dd4c50 100644 --- a/spot/twaalgos/aiger.hh +++ b/spot/twaalgos/aiger.hh @@ -1,5 +1,5 @@ // -*- coding: utf-8 -*- -// Copyright (C) 2020 Laboratoire de Recherche et Développement +// Copyright (C) 2020-21 Laboratoire de Recherche et Développement // de l'Epita (LRDE). // // This file is part of Spot, a model checking library. @@ -21,10 +21,442 @@ #include #include +#include #include +#include +#include + +#include +#include +#include +#include +#include + namespace spot { + class aig; + + typedef std::shared_ptr aig_ptr; + typedef std::shared_ptr const_aig_ptr; + + /// \brief A class representing AIG circuits + /// + /// AIG circuits consist of (named) inputs, (named) outputs, latches which + /// serve as memory, and gates and negations connecting them. + /// AIG circuits can be used to represent controllers, which is currently + /// their sole purpose within spot. + /// AIGs produce a output sequence based on the following rules: + /// 1) All latches are initialised to 0 + /// 2) The next input is read. + /// 3) The output and the state of the latches for the next turn + /// are given by the gates as a function of the current latches and inputs + class SPOT_API aig + { + protected: + const unsigned num_inputs_; + const unsigned num_outputs_; + const unsigned num_latches_; + const std::vector input_names_; + const std::vector output_names_; + unsigned max_var_; + + std::vector next_latches_; + std::vector outputs_; + std::vector> and_gates_; + bdd_dict_ptr dict_; + // Cache the function computed by each variable as a bdd. + // Bidirectional map + std::unordered_map var2bdd_; + std::unordered_map bdd2var_; //uses id + // First anonymous var marking the beginning of variables used + // as latches + int l0_; + + bdd all_ins_; + bdd all_latches_; + + // For simulation + std::vector state_; + + public: + + /// \brief Mark the beginning of a test tranlation + /// + /// Sometimes different encodings produces more or less gates. + /// To improve performances, one can "safe" the current status + /// and revert changes afterwards if needed + using safe_point = std::pair; + using safe_stash = + std::tuple>, + std::vector>, + std::vector>; + + /// \brief Constructing an "empty" aig, knowing only about the + /// necessary inputs, outputs and latches. A bdd_dict can + /// be handed to the circuit in order to allow for verification + /// against other automata after construction + aig(const std::vector& inputs, + const std::vector& outputs, + unsigned num_latches, + bdd_dict_ptr dict = make_bdd_dict()); + + /// \brief Constructing the circuit with generic names. + aig(unsigned num_inputs, unsigned num_outputs, + unsigned num_latches, bdd_dict_ptr dict = make_bdd_dict()); + + ~aig() + { + dict_->unregister_all_my_variables(this); + } + + protected: + /// \brief Register a new literal in both maps + void register_new_lit_(unsigned v, const bdd &b); + void register_latch_(unsigned i, const bdd& b); + void register_input_(unsigned i, const bdd& b); + /// \brief Remove a literal from both maps + void unregister_lit_(unsigned v); + + /// \brief Internal function that split a bdd into a conjunction + /// hoping to increase reusage of gates + void split_cond_(const bdd& b, char so_mode, + std::vector& cond_parts); + + /// \brief Split-off common sub-expressions as cube + bdd accum_common_(const bdd& b) const; + + /// Translate a cube into gates, using split-off optionally + unsigned cube2var_(const bdd& b, const int use_split_off); + + public: + + /// \brief Safe the current state of the circuit + /// \note This does not make a copy, so rolling back to + /// an older safe point invalidates all newer safepoints. + /// Also only concerns the gates, output and next_latch variables + /// will not change + /// This function is semi-public. Make sure you know what you are + /// doing when using it. + safe_point get_safe_point_() const; + + /// \brief roll_back to the saved point. + /// + /// \param sp : The safe_point to revert back to + /// \param do_stash : Whether or not to save the changes to be possibly + /// reapplied later on + /// \note: This function is semi-public. Make sure you know what you are + /// doing when using it. + safe_stash roll_back_(safe_point sp, + bool do_stash = false); + /// \brief Reapply to stored changes on top of a safe_point + /// \note: ss has to be obtained from roll_back_(sp, true) + /// This function is semi-public. Make sure you know what you are + /// doing when using it. + void reapply_(safe_point sp, const safe_stash& ss); + + /// \brief Get the number of outputs + unsigned num_outputs() const + { + return num_outputs_; + } + /// \brief Get the variables associated to the ouputs + /// \note Only available after call to aig::set_output + const std::vector& outputs() const + { + SPOT_ASSERT(std::none_of(outputs_.begin(), outputs_.end(), + [](unsigned o){return o == -1u; })); + return outputs_; + } + /// \brief Get the set of output names + const std::vector& output_names() const + { + return output_names_; + } + + /// \brief Get the number of inputs + unsigned num_inputs() const + { + return num_inputs_; + } + /// \brief Get the set of input names + const std::vector& input_names() const + { + return input_names_; + } + + /// \brief Get the number of latches in the circuit + unsigned num_latches() const + { + return num_latches_; + } + /// \brief Get the variables associated to the state of the latches + /// in the next iteration + /// \note Only available after call to aig::set_next_latch + const std::vector& next_latches() const + { + SPOT_ASSERT(std::none_of(next_latches_.begin(), next_latches_.end(), + [](unsigned o){return o == -1u; })); + return next_latches_; + }; + + /// \brief Get the total number of and gates + unsigned num_gates() const + { + return and_gates_.size(); + }; + /// \brief Access the underlying container + const std::vector>& gates() const + { + return and_gates_; + }; + + /// \brief Maximal variable index currently appearing in the circuit + unsigned max_var() const + { + return max_var_; + }; + + /// \brief Get the variable associated to the ith input + unsigned input_var(unsigned i, bool neg = false) const + { + SPOT_ASSERT(i < num_inputs_); + return (1 + i) * 2 + neg; + } + /// \brief Get the bdd associated to the ith input + bdd input_bdd(unsigned i, bool neg = false) const + { + return aigvar2bdd(input_var(i, neg)); + } + + /// \brief Get the variable associated to the ith latch + unsigned latch_var(unsigned i, bool neg = false) const + { + SPOT_ASSERT(i < num_latches_); + return (1 + num_inputs_ + i) * 2 + neg; + } + /// \brief Get the bdd associated to the ith latch + bdd latch_bdd(unsigned i, bool neg = false) const + { + return aigvar2bdd(latch_var(i, neg)); + } + + /// \brief Get the variable associated to the ith gate + unsigned gate_var(unsigned i, bool neg = false) const + { + SPOT_ASSERT(i < num_gates()); + return (1 + num_inputs_ + num_latches_ + i) * 2 + neg; + } + /// \brief Get the bdd associated to the ith gate + bdd gate_bdd(unsigned i, bool neg = false) const + { + return aigvar2bdd(gate_var(i, neg)); + } + + /// \brief Get the bdd associated to a variable + /// \note Throws if non-existent + bdd aigvar2bdd(unsigned v, bool neg = false) const + { + return neg ? bdd_not(var2bdd_.at(v)) : var2bdd_.at(v); + } + + /// \brief Get the variable associated to a bdd + /// \note Throws if non-existent + unsigned bdd2aigvar(const bdd& b) const + { + return bdd2var_.at(b.id()); + } + + /// \brief Add a bdd to the circuit using if-then-else normal form + unsigned bdd2INFvar(const bdd& b); + + /// \brief Add a bdd to the circuit using isop normal form + unsigned bdd2ISOPvar(const bdd& b, const int use_split_off = 0); + + /// \brief Add a bdd to the circuit + /// Assumes that all bdd's given in c_alt fulfill the same purpose, + /// that is, any of these conditions can be encoded and the + /// corresponding literal returned. + /// Multiple translation options are available whose main + /// goal is to minimize the necessary number of gates. + /// + /// \param method How to translate the bdd. 0: If-then-else normal form, + /// 1: isop normal form, 2: try both and retain smaller + /// \param use_dual Encode the negations of the given bdds and + /// retain the smalles implementation + /// \param use_split_off 0: Use base algo + /// 1: Separate the different types of input signals + /// (like latches, inputs) to increase gate + /// re-usability and retain smallest circuit + /// 2: Actively search for subexpressions the + /// within expressions + unsigned encode_bdd(const std::vector& c_alt, + char method = 1, bool use_dual = false, + int use_split_off = 0); + + /// \brief Just like the vector version but with no alternatives given + unsigned encode_bdd(const bdd& b, + char method = 1, bool use_dual = false, + int use_split_off = 0); + + /// \brief Associate the ith output to the variable v + void set_output(unsigned i, unsigned v); + + /// \brief Associate the ith latch state after update to the variable v + void set_next_latch(unsigned i, unsigned v); + + static constexpr unsigned aig_true() noexcept + { + return 1; + }; + + static constexpr unsigned aig_false() noexcept + { + return 0; + }; + + /// \brief Negate a variable + unsigned aig_not(unsigned v); + + /// \brief Compute AND of v1 and v2 + unsigned aig_and(unsigned v1, unsigned v2); + + /// \brief Computes the AND of all vars + /// \note This function modifies the given vector to only contain the + /// result (at position zero) after the call + unsigned aig_and(std::vector& vs); + + /// \brief Computes the OR of v1 and v2 + unsigned aig_or(unsigned v1, unsigned v2); + + /// \brief Computes the or of all vars + /// \note This function modifies the given vector to only contain the + /// result after call + unsigned aig_or(std::vector& vs); + + /// \brief Returns the positive form of the given variable + unsigned aig_pos(unsigned v); + + /// \brief Instead of successively adding bdds to the circuit, + /// one can also pass a vector of all bdds needed to the circuit. + /// In this case additional optimization steps are taken to minimize + /// the size of the circuit + /// \note This can be costly and did not bring about any advantages + /// in the SYNTCOMP cases + void encode_all_bdds(const std::vector& all_bdd); + + /// \brief Create a circuit from an aag file with restricted syntax. + /// + /// \note Additional constraints are: + /// - Gates have to appear in an ordered fashion. + /// - Inputs are expected to have variable numbers from 2-2*n_i+1 + /// with n_i being the number of inputs + /// - Latches can not be named + static aig_ptr + parse_aag(const std::string& aig_file, + bdd_dict_ptr dict = make_bdd_dict()); + + static aig_ptr + parse_aag(const char* data, + const std::string& filename, + bdd_dict_ptr dict = make_bdd_dict()); + + static aig_ptr + parse_aag(std::istream& iss, + const std::string& filename, + bdd_dict_ptr dict = make_bdd_dict()); + + /// \brief Transform the circuit onto an equivalent monitor + /// \param keepsplit If as_automaton(true) is the same as + /// split_2step(as_automaton(false), outputs) + /// \note The complexity is exponential in the number of inputs! + twa_graph_ptr as_automaton(bool keepsplit = false) const; + + /// \brief Gives access to the current state of the circuit. + /// + /// Corresponds to a vector of booleans holding the truth value + /// for each literal. Note that within the vector we have the truth + /// value of a literal and its negation, so sim_state()[2*i+1] is + /// always the negation of sim_state()[2*i]. + /// The variable index can be obtained using + /// input_var, latch_var or outputs + const std::vector& circ_state() const + { + SPOT_ASSERT(state_.size() == max_var_ + 2 + && "State vector does not have the correct size.\n" + "Forgot to initialize?"); + return state_; + } + + /// \brief Access to the state of a specific variable + bool circ_state_of(unsigned var) const + { + SPOT_ASSERT(var <= max_var_ + 1 + && "Variable out of range"); + return circ_state()[var]; + } + + /// \brief (Re)initialize the stepwise evaluation of the circuit. + /// This sets all latches to 0 and clears the output + void circ_init(); + + /// \brief Performs the next discrete step of the circuit, + /// based on the inputs. + /// + /// Updates the state of the aig such that circ_state holds the + /// values of output and latches AFTER reading the given input + /// \param inputs : Vector of booleans with size num_inputs() + void circ_step(const std::vector& inputs); + + }; + + /// \brief Convert a strategy into an aig relying on the transformation + /// described by mode. + /// \param mode This param has to be of the form + /// ite|isop|both [+dc][+dual][+so0|+so1|+so2|+so3] + /// Where ite means encoded via if-then-else normalform + /// isop means encoded via irreducible sum of products + /// both means trying both encodings and keep the smaller circuit. + /// +dc is optional and tries to take advantage of "do not care" + /// outputs to minimize the circuit. + /// +dual is optional and indicates that the algorithm + /// should also try to encode the negation to generate smaller + /// circuits. + /// +sox indicates that the conditions can be seperated into + /// blocks with so0 being no separation, so1 separation into + /// input/latches/gates (isop only) and so2 tries to seek + /// common subformulas. + SPOT_API aig_ptr + strategy_to_aig(const const_twa_graph_ptr& aut, const char* mode); + + /// \brief Convert multiple strategies into an aig relying on + /// the transformation described by mode. + /// \note The states of each strategy are represented by a block of latches + /// not affected by the others. For this to work in a general setting, + /// the outputs must be disjoint. + SPOT_API aig_ptr + strategies_to_aig(const std::vector& strat_vec, + const char* mode); + + /// \brief Like above, but explicitly handing over which propositions + /// are inputs and outputs and does therefore not rely on the + /// named property "synthesis-outputs" + SPOT_API aig_ptr + strategy_to_aig(const twa_graph_ptr& aut, const char *mode, + const std::vector& ins, + const std::vector& outs); + + /// \brief Like above, but explicitly handing over the propositions + SPOT_API aig_ptr + strategies_to_aig(const std::vector& strat_vec, + const char* mode, + const std::vector& ins, + const std::vector>& outs); + + /// \brief Print the aig to stream in AIGER format + SPOT_API std::ostream& + print_aiger(std::ostream& os, const_aig_ptr circuit); + /// \ingroup twa_io /// \brief Encode and print an automaton as an AIGER circuit. /// @@ -45,12 +477,23 @@ namespace spot /// Correct graphs are generated by spot::unsplit_2step /// /// - /// \param os The output stream to print on. - /// \param aut The automaton to output. - /// \param mode Determines how the automaton is encoded. - /// "ISOP" Uses DNF. - /// "ITE" Uses the "if-then-else" normal-form + /// \param os The output stream to print on. + /// \param aut The automaton to output. + /// \param mode This param has to be of the form + /// ite|isop|both [+dc][+dual][+so0|+so1|+so2|+so3] + /// Where ite means encoded via if-then-else normalform + /// isop means encoded via irreducible sum of products + /// both means trying both encodings and keep the smaller circuit. + /// +dc is optional and tries to take advantage of "do not care" + /// outputs to minimize the circuit. + /// +dual is optional and indicates that the algorithm + /// should also try to encode the negation to generate smaller + /// circuits. + /// +sox indicates that the conditions can be seperated into + /// blocks with so0 being no separation, so1 separation into + /// input/latches/gates (isop only) and so2 tries to + /// seek common subformulas. SPOT_API std::ostream& - print_aiger(std::ostream& os, const const_twa_ptr& aut, + print_aiger(std::ostream& os, const const_twa_graph_ptr& aut, const char* mode); } diff --git a/tests/Makefile.am b/tests/Makefile.am index b7ec460aa..21c33979f 100644 --- a/tests/Makefile.am +++ b/tests/Makefile.am @@ -387,6 +387,7 @@ TESTS_python = \ python/_aux.ipynb \ python/accparse2.py \ python/alarm.py \ + python/aiger.py \ python/alternating.py \ python/bdddict.py \ python/bdditer.py \ diff --git a/tests/core/ltlsynt.test b/tests/core/ltlsynt.test index 04a65c232..33e733d3a 100644 --- a/tests/core/ltlsynt.test +++ b/tests/core/ltlsynt.test @@ -74,28 +74,115 @@ diff out exp cat >exp < GFb' --aiger=ISOP >out +ltlsynt --ins=a --outs=b -f 'GFa <-> GFb' --aiger=isop >out +diff out exp + +cat >exp < GFb' --aiger=isop+dc >out +diff out exp + +cat >exp < GFb' --aiger=isop+ud >out +diff out exp + +cat >exp < GFb' --aiger=isop+sub1 >out +diff out exp + +cat >exp < GFb' --aiger=isop+sub2 >out +diff out exp + +cat >exp < GFb' --aiger=isop,isop+dc,isop+ud >out diff out exp cat >exp < GFb' --aiger=ITE >out +ltlsynt --ins=a --outs=b -f 'GFa <-> GFb' --aiger=ite >out diff out exp cat >exp < GFb' --aiger=ite+ud+dc >out +diff out exp + +cat >exp < (GFb & GFc)' --aiger=Isop >out +ltlsynt --ins=a --outs=b,c -f 'GFa <-> (GFb & GFc)' --aiger=isop >out +diff out exp + +cat >exp < (GFb & GFc)' --aiger=isop+dc >out diff out exp cat >exp <. + +import spot, buddy + +strats = (("""HOA: v1 +States: 4 +Start: 0 +AP: 3 "a" "b" "c" +acc-name: all +Acceptance: 0 t +properties: trans-labels explicit-labels state-acc deterministic +--BODY-- +State: 0 +[0&!1&2] 1 +[!0&!1&2] 1 +State: 1 +[0&!1] 2 +[!0&!1] 1 +State: 2 +[0&1] 3 +[!0&1] 3 +State: 3 +[0&!2] 0 +[!0&!2] 3 +--END-- +""", (("a"), ("b", "c"))), +("""HOA: v1 +States: 4 +Start: 0 +AP: 7 "i0" "i1" "i2" "o0" "o1" "o2" "o3" +acc-name: all +Acceptance: 0 t +properties: trans-labels explicit-labels state-acc +--BODY-- +State: 0 +[!0] 1 +[0&!1&!3&!4&5&!6] 2 +[0&1&!3&4&5&!6] 2 +State: 1 +[t] 1 +State: 2 +[!1&!2&!3&!4&5&!6] 2 +[!0&!1&!3&!4&5&!6] 2 +[1&!2&!3&4&5&!6] 2 +[!0&1&!3&4&5&!6] 2 +[0&!1&2&3&!4&5&!6] 3 +[0&1&2&3&4&5&!6] 3 +State: 3 +[!0&!2&!3&!4&!5&6] 3 +[0&!2&3&!4&!5&6] 2 +[!0&2&!3&4&!5&6] 3 +[0&2&3&4&!5&6] 2 +--END--""", ([f"i{i}" for i in range(3)],[f"o{i}" for i in range(4)])), +("""HOA: v1 +States: 136 +Start: 0 +AP: 11 "i3" "i4" "o4" "o5" "i0" "i1" "i2" "o0" "o1" "o2" "o3" +acc-name: all +Acceptance: 0 t +properties: trans-labels explicit-labels state-acc +--BODY-- +State: 0 +[!4] 1 +[!2&!3&4&!5&!7&!8&9&!10] 2 +[!2&!3&4&5&!7&8&9&!10] 2 +State: 1 +[t] 1 +State: 2 +[!0&!1&!2&!3&!5&!6&!7&!8&9&!10] 2 +[1&!2&!3&!4&!5&!7&!8&9&!10] 2 +[!0&!2&!3&!4&5&!6&!7&8&9&!10] 2 +[1&!2&!3&!4&5&!7&8&9&!10] 2 +[!0&1&!2&!3&4&!5&!6&7&!8&9&!10] 3 +[0&!1&!2&!3&!4&!5&!7&!8&9&!10] 4 +[0&!1&!2&!3&4&!5&!6&7&!8&9&!10] 5 +[0&1&!2&!3&4&!5&7&!8&9&!10] 6 +[!0&!1&!2&!3&!4&!5&6&!7&!8&9&!10] 7 +[!0&!1&!2&!3&4&!5&6&7&!8&9&!10] 8 +[!0&1&!2&!3&4&!5&6&7&!8&9&!10] 9 +[0&!1&!2&!3&4&!5&6&7&!8&9&!10] 10 +[!0&!1&!2&!3&4&5&!6&7&8&9&!10] 11 +[!0&1&!2&!3&4&5&!6&7&8&9&!10] 3 +[0&!1&!2&!3&!4&5&!7&8&9&!10] 4 +[0&!1&!2&!3&4&5&!6&7&8&9&!10] 5 +[0&1&!2&!3&4&5&7&8&9&!10] 6 +[!0&!1&!2&!3&!4&5&6&!7&8&9&!10] 7 +[!0&!1&!2&!3&4&5&6&7&8&9&!10] 8 +[!0&1&!2&!3&4&5&6&7&8&9&!10] 9 +[0&!1&!2&!3&4&5&6&7&8&9&!10] 10 +State: 3 +[!0&!1&!2&3&!5&!6&!7&!8&!9&!10] 12 +[0&!1&!2&3&!4&!7&!8&!9&!10] 12 +[!0&1&!2&3&!5&!6&!7&8&!9&!10] 12 +[0&1&!2&3&!4&!7&8&!9&!10] 12 +[0&!1&2&!3&4&!5&!6&7&8&!9&!10] 13 +[!0&!1&!2&3&!4&6&!7&!8&!9&!10] 14 +[!0&!1&!2&!3&4&!5&6&7&8&!9&10] 15 +[!0&1&!2&3&!4&6&!7&8&!9&!10] 14 +[0&1&!2&3&4&6&7&8&!9&!10] 16 +[!0&!1&!2&3&!4&5&!6&!7&!8&!9&!10] 17 +[!0&1&!2&3&!4&5&!6&!7&8&!9&!10] 17 +[0&1&!2&3&4&5&!6&7&8&!9&!10] 18 +[!0&1&!2&3&4&5&6&7&8&!9&!10] 19 +[0&1&!2&3&4&!5&!6&7&8&!9&!10] 20 +[!0&1&!2&3&4&!5&6&7&8&!9&!10] 21 +[!0&!1&!2&3&4&5&!6&7&!8&!9&!10] 22 +[!0&1&!2&3&4&5&!6&7&8&!9&!10] 22 +[!0&!1&!2&3&4&5&6&7&!8&!9&!10] 19 +[0&!1&!2&3&4&6&7&!8&!9&!10] 16 +[0&!1&!2&3&4&5&!6&7&!8&!9&!10] 18 +State: 4 +[!0&!1&!2&!3&!5&!6&!7&!8&9&!10] 2 +[!0&!2&!3&!4&!5&!6&!7&!8&9&!10] 2 +[!0&!2&!3&!4&5&!6&!7&8&9&!10] 2 +[0&!2&!3&!4&!5&!7&!8&9&!10] 4 +[0&!2&!3&4&!5&!6&7&!8&9&!10] 5 +[!0&!2&!3&!4&!5&6&!7&!8&9&!10] 7 +[!0&!2&!3&4&!5&6&7&!8&9&!10] 8 +[0&!2&!3&4&!5&6&7&!8&9&!10] 10 +[!0&!2&!3&4&5&!6&7&8&9&!10] 11 +[0&!2&!3&!4&5&!7&8&9&!10] 4 +[0&!2&!3&4&5&!6&7&8&9&!10] 5 +[!0&!2&!3&!4&5&6&!7&8&9&!10] 7 +[!0&!2&!3&4&5&6&7&8&9&!10] 8 +[0&!2&!3&4&5&6&7&8&9&!10] 10 +[!0&1&!2&!3&4&!5&!6&7&!8&9&!10] 11 +State: 5 +[!0&!1&!2&3&!5&!6&!7&!8&!9&!10] 12 +[!0&1&!2&3&!5&!6&!7&8&!9&!10] 12 +[0&2&!3&4&!5&!6&7&8&!9&!10] 13 +[!0&!2&!3&4&!5&6&7&8&!9&10] 15 +[0&!1&2&!3&!4&6&!7&8&!9&!10] 23 +[!0&1&!2&3&!4&5&!6&!7&8&!9&!10] 17 +[0&!1&2&!3&!4&5&!6&!7&8&!9&!10] 24 +[!0&1&!2&!3&!4&5&6&!7&8&!9&10] 25 +[!0&1&!2&!3&4&5&6&7&8&!9&10] 26 +[0&!1&2&!3&4&5&6&7&8&!9&!10] 27 +[!0&1&!2&!3&!4&!5&6&!7&8&!9&10] 28 +[0&!1&2&!3&4&!5&6&7&8&!9&!10] 29 +[0&2&!3&!4&!5&!6&!7&8&!9&!10] 30 +[!0&!1&2&!3&!4&5&!6&!7&!8&!9&!10] 24 +[!0&!1&2&!3&!4&6&!7&!8&!9&!10] 23 +[0&1&2&!3&!4&6&!7&8&!9&!10] 31 +[0&1&2&!3&4&6&7&8&!9&!10] 32 +[0&!1&2&!3&4&5&!6&7&8&!9&!10] 33 +[0&1&2&!3&4&5&!6&7&8&!9&!10] 34 +[!0&1&!2&!3&4&5&!6&7&!8&!9&10] 26 +[!0&!1&2&!3&4&5&6&7&!8&!9&!10] 27 +[0&1&2&!3&!4&5&!6&!7&8&!9&!10] 35 +[!0&!1&2&!3&4&5&!6&7&!8&!9&!10] 33 +State: 6 +[!0&!1&!2&3&!5&!6&!7&!8&!9&!10] 12 +[!0&1&!2&3&!5&!6&!7&8&!9&!10] 12 +[0&1&!2&3&!4&!7&8&!9&!10] 12 +[0&!1&2&!3&4&!5&!6&7&8&!9&!10] 13 +[0&1&2&!3&4&!5&!6&7&8&!9&!10] 36 +[!0&!1&!2&!3&4&!5&6&7&8&!9&10] 15 +[!0&1&!2&3&!4&6&!7&8&!9&!10] 14 +[!0&1&!2&!3&4&!5&6&7&8&!9&10] 37 +[0&!1&2&!3&!4&6&!7&8&!9&!10] 23 +[0&!1&2&!3&4&!5&6&7&8&!9&!10] 38 +[0&1&!2&3&4&6&7&8&!9&!10] 16 +[!0&!1&!2&3&!4&5&!6&!7&!8&!9&!10] 17 +[!0&!1&2&!3&4&5&!6&7&!8&!9&!10] 39 +[!0&1&!2&3&!4&5&!6&!7&8&!9&!10] 17 +[!0&1&!2&3&4&5&!6&7&8&!9&!10] 40 +[0&!1&2&!3&!4&5&!6&!7&8&!9&!10] 24 +[0&!1&2&!3&4&5&!6&7&8&!9&!10] 39 +[0&1&!2&3&4&5&!6&7&8&!9&!10] 18 +[!0&!1&!2&!3&!4&5&6&!7&8&!9&10] 25 +[!0&!1&!2&!3&4&5&6&7&8&!9&10] 26 +[!0&1&!2&3&4&5&6&7&8&!9&!10] 19 +[0&!1&2&!3&4&5&6&7&8&!9&!10] 27 +[!0&!1&!2&!3&!4&!5&6&!7&8&!9&10] 28 +[0&!1&2&!3&!4&!5&!6&!7&8&!9&!10] 30 +State: 7 +[!0&!1&!2&!3&!5&!6&!7&!8&9&!10] 2 +[1&!2&!3&!4&!5&!6&!7&!8&9&!10] 2 +[!0&!2&!3&!4&5&!6&!7&8&9&!10] 2 +[1&!2&!3&!4&5&!6&!7&8&9&!10] 2 +[0&!1&!2&!3&!4&!5&!6&!7&!8&9&!10] 4 +[0&1&!2&!3&4&!5&!6&7&!8&9&!10] 6 +[!2&!3&!4&!5&6&!7&!8&9&!10] 7 +[!0&!2&!3&4&!5&6&7&!8&9&!10] 8 +[1&!2&!3&4&!5&6&7&!8&9&!10] 8 +[!0&!2&!3&4&5&!6&7&8&9&!10] 11 +[0&!1&!2&!3&!4&5&!6&!7&8&9&!10] 4 +[0&1&!2&!3&4&5&!6&7&8&9&!10] 6 +[!2&!3&!4&5&6&!7&8&9&!10] 7 +[!0&!2&!3&4&5&6&7&8&9&!10] 8 +[1&!2&!3&4&5&6&7&8&9&!10] 8 +[!0&1&!2&!3&4&!5&!6&7&!8&9&!10] 11 +[0&!1&!2&!3&4&!5&!6&7&!8&9&!10] 41 +[0&!1&!2&!3&4&5&!6&7&8&9&!10] 41 +[0&!1&!2&!3&4&!5&6&7&!8&9&!10] 42 +[0&!1&!2&!3&4&5&6&7&8&9&!10] 42 +State: 8 +[!0&!1&!2&3&!5&!6&!7&!8&!9&!10] 12 +[!1&!2&3&!4&!5&!6&!7&!8&!9&!10] 12 +[!0&1&!2&3&!5&!6&!7&8&!9&!10] 12 +[1&!2&3&!4&!5&!6&!7&8&!9&!10] 12 +[0&2&!3&4&!5&!6&7&8&!9&!10] 13 +[!0&!2&!3&4&!5&6&7&8&!9&10] 15 +[0&!1&!2&3&!4&5&!6&!7&!8&!9&!10] 17 +[!0&1&2&!3&4&5&!6&7&!8&!9&!10] 39 +[1&!2&3&!4&5&!6&!7&8&!9&!10] 17 +[0&2&!3&4&5&!6&7&8&!9&!10] 39 +[!0&!1&!2&!3&!4&5&6&!7&8&!9&10] 25 +[!0&!2&!3&!4&!5&6&!7&8&!9&10] 28 +[1&!2&!3&!4&!5&6&!7&8&!9&10] 28 +[0&!1&!2&!3&!4&!5&6&!7&8&!9&10] 43 +[0&!1&!2&!3&4&!5&6&7&8&!9&10] 44 +[0&1&!2&!3&4&!5&6&7&8&!9&10] 45 +[!0&!1&!2&!3&!4&5&!6&!7&!8&!9&10] 25 +[!0&!1&!2&!3&4&5&!6&7&!8&!9&10] 46 +[!0&!1&!2&!3&4&5&6&7&8&!9&10] 46 +[1&!2&!3&!4&5&6&!7&8&!9&10] 47 +[!0&1&!2&!3&4&5&6&7&8&!9&10] 48 +[0&!1&!2&!3&!4&5&6&!7&8&!9&10] 49 +[0&!1&!2&!3&4&5&6&7&8&!9&10] 50 +[0&1&!2&!3&4&5&6&7&8&!9&10] 51 +State: 9 +[!0&!1&!2&3&!5&!6&!7&!8&!9&!10] 12 +[!1&!2&3&!4&!5&!6&!7&!8&!9&!10] 12 +[!0&1&!2&3&!5&!6&!7&8&!9&!10] 12 +[1&!2&3&!4&!5&!6&!7&8&!9&!10] 12 +[0&!1&2&!3&4&!5&!6&7&8&!9&!10] 13 +[!0&!1&!2&!3&4&!5&6&7&8&!9&10] 15 +[!0&1&!2&3&!4&6&!7&8&!9&!10] 14 +[!0&1&!2&!3&4&!5&6&7&8&!9&10] 37 +[0&!1&2&!3&!4&6&!7&8&!9&!10] 23 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+[!0&!1&!2&!3&!4&5&6&!7&8&9&!10] 7 +[0&2&!3&4&!5&!6&7&8&!9&!10] 13 +[!0&!2&!3&4&!5&6&7&8&!9&10] 15 +[0&!1&2&!3&!4&!5&6&!7&8&!9&!10] 23 +[!0&1&!2&!3&4&!5&!6&7&!8&9&!10] 11 +[0&!1&!2&!3&4&5&!6&7&8&9&!10] 41 +[0&!1&!2&!3&4&5&6&7&8&!9&10] 66 +[0&!1&2&!3&4&!5&6&7&8&!9&!10] 29 +[!0&!1&!2&!3&4&5&6&7&8&9&!10] 70 +[0&1&!2&!3&!4&5&!6&!7&8&9&!10] 89 +[0&1&!2&!3&4&5&!6&7&8&9&!10] 83 +[!0&1&!2&!3&!4&5&6&!7&8&9&!10] 90 +[!0&1&!2&!3&4&5&6&7&8&9&!10] 84 +[0&1&2&!3&!4&!5&!6&!7&8&!9&!10] 30 +[!0&1&!2&!3&!4&!5&6&!7&!8&9&!10] 90 +[0&1&!2&!3&4&!5&6&7&8&!9&10] 88 +[0&1&2&!3&!4&!5&6&!7&8&!9&!10] 31 +[!0&!1&!2&!3&4&!5&!6&7&!8&!9&10] 2 +[0&!1&!2&!3&!4&5&6&!7&8&9&!10] 99 +[0&1&!2&!3&!4&5&6&!7&8&9&!10] 133 +[0&1&!2&!3&4&5&6&7&8&9&!10] 134 +State: 132 +[!0&!1&!2&3&!5&!6&!7&!8&!9&!10] 12 +[!1&!2&3&!4&!5&!6&!7&!8&!9&!10] 12 +[!0&1&!2&3&!5&!6&!7&8&!9&!10] 12 +[0&2&!3&4&!5&!6&7&8&!9&!10] 13 +[!0&!1&!2&3&!4&!5&6&!7&!8&!9&!10] 14 +[!0&!2&!3&4&!5&6&7&8&!9&10] 15 +[!0&1&!2&3&!4&!5&6&!7&8&!9&!10] 14 +[0&!1&2&!3&!4&!5&6&!7&8&!9&!10] 23 +[!0&!1&!2&3&!4&5&!6&!7&!8&!9&!10] 17 +[!0&!1&2&!3&4&5&!6&7&!8&!9&!10] 39 +[!0&1&!2&3&!4&5&!6&!7&8&!9&!10] 17 +[!0&1&!2&3&4&5&!6&7&8&!9&!10] 40 +[0&!1&2&!3&!4&5&!6&!7&8&!9&!10] 24 +[0&!1&2&!3&4&5&!6&7&8&!9&!10] 39 +[!0&!1&!2&!3&!4&5&6&!7&8&!9&10] 25 +[0&!1&!2&!3&4&!5&6&7&8&!9&10] 44 +[0&1&!2&!3&!4&!5&!6&!7&!8&!9&10] 87 +[0&1&!2&!3&!4&!5&6&!7&8&!9&10] 87 +[0&1&!2&!3&4&!5&6&7&8&!9&10] 88 +[!0&!1&!2&!3&4&5&6&7&8&!9&10] 46 +[!0&1&!2&!3&!4&5&6&!7&8&!9&10] 47 +[!0&1&!2&!3&4&5&6&7&8&!9&10] 48 +[0&1&!2&3&4&5&!6&7&8&!9&!10] 55 +[0&!1&!2&!3&!4&5&6&!7&8&!9&10] 49 +[0&!1&!2&!3&4&5&6&7&8&!9&10] 50 +[0&1&!2&!3&!4&5&!6&!7&!8&!9&10] 118 +[0&1&!2&!3&5&6&!7&8&!9&10] 118 +State: 133 +[!0&!1&!2&!3&!5&!6&!7&!8&9&!10] 2 +[!0&!2&!3&!4&!5&!6&!7&!8&9&!10] 2 +[!0&!2&!3&!4&5&!6&!7&8&9&!10] 2 +[0&!1&!2&!3&!4&!5&!6&!7&!8&9&!10] 4 +[!0&!1&!2&!3&!4&!5&6&!7&!8&9&!10] 7 +[!0&!2&!3&4&5&!6&7&8&9&!10] 11 +[0&!1&!2&!3&!4&5&!6&!7&8&9&!10] 4 +[!0&!1&!2&!3&!4&5&6&!7&8&9&!10] 7 +[!0&1&!2&!3&4&!5&!6&7&!8&9&!10] 11 +[0&!1&!2&!3&4&!5&!6&7&!8&9&!10] 41 +[0&!1&!2&!3&4&5&!6&7&8&9&!10] 41 +[!0&!1&!2&!3&4&5&6&7&8&9&!10] 70 +[0&1&!2&!3&!4&5&!6&!7&8&9&!10] 89 +[0&1&!2&!3&4&5&!6&7&8&9&!10] 83 +[!0&1&!2&!3&!4&5&6&!7&8&9&!10] 90 +[!0&1&!2&!3&4&5&6&7&8&9&!10] 84 +[!0&1&!2&!3&!4&!5&6&!7&!8&9&!10] 90 +[!0&1&!2&!3&4&!5&6&7&!8&9&!10] 84 +[0&!1&!2&!3&!4&!5&6&!7&!8&9&!10] 99 +[0&1&!2&!3&!4&!5&!6&!7&!8&9&!10] 89 +[0&1&!2&!3&4&!5&!6&7&!8&9&!10] 83 +[!0&!1&!2&!3&4&!5&6&7&!8&9&!10] 70 +[0&!1&!2&!3&4&!5&6&7&!8&9&!10] 112 +[0&!1&!2&!3&!4&5&6&!7&8&9&!10] 99 +[0&!1&!2&!3&4&5&6&7&8&9&!10] 112 +[0&1&!2&!3&!4&5&6&!7&8&9&!10] 133 +[0&1&!2&!3&4&5&6&7&8&9&!10] 134 +[0&1&!2&!3&!4&!5&6&!7&!8&9&!10] 133 +[0&1&!2&!3&4&!5&6&7&!8&9&!10] 134 +State: 134 +[!0&!1&!2&3&!5&!6&!7&!8&!9&!10] 12 +[!1&!2&3&!4&!5&!6&!7&!8&!9&!10] 12 +[!0&1&!2&3&!5&!6&!7&8&!9&!10] 12 +[1&!2&3&!4&!5&!6&!7&8&!9&!10] 12 +[0&2&!3&4&!5&!6&7&8&!9&!10] 13 +[!0&!1&!2&3&!4&!5&6&!7&!8&!9&!10] 14 +[!0&!2&!3&4&!5&6&7&8&!9&10] 15 +[!0&1&!2&3&!4&6&!7&8&!9&!10] 14 +[0&!1&2&!3&!4&6&!7&8&!9&!10] 23 +[!0&!1&!2&3&!4&5&!6&!7&!8&!9&!10] 17 +[!0&1&!2&3&!4&5&!6&!7&8&!9&!10] 17 +[0&!1&2&!3&!4&5&!6&!7&8&!9&!10] 24 +[!0&!1&!2&!3&!4&5&6&!7&8&!9&10] 25 +[0&!1&2&!3&4&5&6&7&8&!9&!10] 27 +[0&!1&2&!3&4&!5&6&7&8&!9&!10] 29 +[0&1&2&!3&!4&5&!6&!7&8&!9&!10] 67 +[!0&!1&!2&!3&4&5&6&7&8&!9&10] 46 +[!0&!1&!2&3&4&5&!6&7&!8&!9&!10] 22 +[!0&1&!2&3&4&5&!6&7&8&!9&!10] 22 +[0&!1&2&!3&4&5&!6&7&8&!9&!10] 33 +[!0&1&!2&!3&4&5&6&7&8&!9&10] 122 +[0&1&2&!3&!4&6&!7&8&!9&!10] 100 +[0&1&!2&!3&4&!5&6&7&8&!9&10] 82 +[0&1&2&!3&4&5&!6&7&8&!9&!10] 135 +[0&1&2&!3&4&5&6&7&8&!9&!10] 68 +State: 135 +[0&!1&!2&!3&!4&!5&!7&!8&9&!10] 4 +[!0&!1&!2&!3&!4&!5&6&!7&!8&9&!10] 7 +[!0&!2&!3&4&5&!6&7&8&9&!10] 11 +[!0&!1&!2&3&!5&!6&!7&!8&!9&!10] 12 +[0&1&!2&3&!4&!5&!7&8&!9&!10] 12 +[1&!2&3&!4&!5&!6&!7&8&!9&!10] 12 +[!0&!2&!3&4&!5&6&7&8&!9&10] 15 +[!0&1&!2&3&!4&!5&6&!7&8&!9&!10] 14 +[0&1&!2&3&4&!5&6&7&8&!9&!10] 16 +[!0&!1&!2&3&!4&5&!6&!7&!8&!9&!10] 17 +[!0&1&!2&3&!4&5&!6&!7&8&!9&!10] 17 +[!0&!1&!2&!3&!4&5&6&!7&8&!9&10] 25 +[!0&!2&!3&4&5&6&7&8&!9&10] 26 +[1&!2&!3&4&5&6&7&8&!9&10] 26 +[!0&1&!2&!3&4&!5&!6&7&!8&9&!10] 11 +[0&!1&!2&!3&4&!5&!6&7&!8&9&!10] 41 +[0&1&!2&3&4&!5&!6&7&8&!9&!10] 20 +[0&!1&!2&!3&4&!5&6&7&8&!9&10] 44 +[0&!1&!2&!3&4&5&!6&7&8&9&!10] 41 +[0&!1&!2&!3&4&5&6&7&8&!9&10] 66 +[0&!1&!2&3&!4&5&!7&!8&!9&!10] 53 +[0&1&!2&3&!4&5&!7&8&!9&!10] 53 +[!0&1&!2&3&!4&5&6&!7&8&!9&!10] 76 +[0&1&!2&!3&4&5&!6&7&!8&!9&10] 26 +--END--""", ([f"i{i}" for i in range(5)],[f"o{i}" for i in range(6)]))) + +for strat_string, (ins_str, outs_str) in strats: + strat = spot.automaton(strat_string) + + ins = buddy.bddtrue + outs = buddy.bddtrue + + for ain in ins_str: + ins &= buddy.bdd_ithvar(strat.register_ap(ain)) + for aout in outs_str: + outs &= buddy.bdd_ithvar(strat.register_ap(aout)) + + spot.set_synthesis_outputs(strat, outs) + strat_s = spot.split_2step(strat, ins, outs, False, False) + + for m in ["isop", "ite", "both"]: + for ss in [""] + [f"+sub{ii}" for ii in range(3)]: + for ddx in ["", "+dc"]:# todo prob here + for uud in ["", "+ud"]: + aig = spot.strategy_to_aig(strat, m+ss+ddx+uud) + strat2_s = aig.as_automaton(True) + if not spot.is_mealy_specialization(strat_s, strat2_s): + print(f"Mode is {m+ss+ddx+uud}") + print(f"""Strat is \n{strat_s.to_str("hoa")}""") + print(f"""Aig as aut is \n{strat2_s.to_str("hoa")}""") + assert 0 + + +# Check stepwise simulation +strat_string, (ins_str, outs_str) = strats[0] +strat = spot.automaton(strat_string) + +ins = buddy.bddtrue +outs = buddy.bddtrue + +for ain in ins_str: + ins &= buddy.bdd_ithvar(strat.register_ap(ain)) +for aout in outs_str: + outs &= buddy.bdd_ithvar(strat.register_ap(aout)) + +spot.set_synthesis_outputs(strat, outs) +aig = spot.strategy_to_aig(strat, "isop") + +ins = [True, False, False, False, True, True, True, True, True, True] +exp_latches = [(False, False), + (True, False), + (True, False), + (True, False), + (True, False), + (False, True), + (True, True), + (False, False), + (True, False)] + +aig.circ_init() + +for (i, e_latch) in zip(ins, exp_latches): + # print(f"{(aig.circ_state()[4], aig.circ_state()[6])},") + if (aig.circ_state()[4], aig.circ_state()[6]) != e_latch: + print("expected ", e_latch, " got ", + (aig.circ_state()[4], aig.circ_state()[6])) + aig.circ_step([i]) + + + +