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Add the "don't care" simulation

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* src/tgba/bddprint.cc, src/tgba/bddprint.hh: Add bdd_print_isop
that prints the bdd into a Irreductible Sum Of Product.
* src/tgbaalgos/dupexp.cc, src/tgbaalgos/dupexp.hh: Add a way to
know which states (in the input) is which (in the result).
* src/tgbaalgos/simulation.cc, src/tgbaalgos/simulation.hh: Add
the Don't Care Simulation and the Don't Care Iterated Simulation.
* src/tgbatest/ltl2tgba.cc, src/tgbatest/spotlbtt.test,
src/tgbatest/Makefile.am, src/tgbatest/sim.test: Test them.
* bench/ltl2tgba/algorithms, bench/ltl2tgba/README,
bench/ltl2tgba/algorithms: Add a way to bench the don't care
simulation.
This commit is contained in:
Thomas Badie 2012-09-27 16:45:40 +02:00 • committed by Alexandre Duret-Lutz
parent 5796114e37
commit 08c77318ae
12 changed files with 1171 additions and 76 deletions
Download patch file Download diff file Expand all files Collapse all files

66
src/tgbatest/ltl2tgba.cc
View file

@ -216,6 +216,8 @@ syntax(char* prog)
<< std::endl
<< " -RIS iterate both direct and reverse simulations"
<< std::endl
<< " -RDCS reduce the automaton with direct simulation"
<< std::endl
<< " -Rm attempt to WDBA-minimize the automaton" << std::endl
<< std::endl
<< " -RM attempt to WDBA-minimize the automaton unless the "
@ -314,6 +316,17 @@ syntax(char* prog)
exit(2);
}
static int
to_int(const char* s)
{
char* endptr;
int res = strtol(s, &endptr, 10);
if (*endptr)
return -1;
return res;
}
int
main(int argc, char** argv)
{
@ -374,6 +387,9 @@ main(int argc, char** argv)
bool reduction_dir_sim = false;
bool reduction_rev_sim = false;
bool reduction_iterated_sim = false;
bool reduction_dont_care_sim = false;
int limit_dont_care_sim = 0;
bool reduction_iterated_dont_care_sim = false;
spot::tgba* temp_dir_sim = 0;
bool ta_opt = false;
bool tgta_opt = false;
@ -382,7 +398,8 @@ main(int argc, char** argv)
bool opt_with_artificial_livelock = false;
spot::tgba* temp_rev_sim = 0;
spot::tgba* temp_iterated_sim = 0;
spot::tgba* temp_dont_care_sim = 0;
spot::tgba* temp_dont_care_iterated_sim = 0;
for (;;)
{
@ -721,6 +738,18 @@ main(int argc, char** argv)
{
reduction_iterated_sim = true;
}
else if (!strncmp(argv[formula_index], "-RDCS", 5))
{
reduction_dont_care_sim = true;
if (argv[formula_index][5] == '=')
limit_dont_care_sim = to_int(argv[formula_index] + 6);
}
else if (!strncmp(argv[formula_index], "-RDCIS", 6))
{
reduction_iterated_dont_care_sim = true;
if (argv[formula_index][6] == '=')
limit_dont_care_sim = to_int(argv[formula_index] + 7);
}
else if (!strcmp(argv[formula_index], "-rL"))
{
simpltl = true;
@ -1131,6 +1160,9 @@ main(int argc, char** argv)
// When the minimization succeed, simulation is useless.
reduction_dir_sim = false;
reduction_rev_sim = false;
reduction_iterated_dont_care_sim = false;
reduction_dont_care_sim = false;
reduction_iterated_sim = false;
assume_sba = true;
}
}
@ -1153,6 +1185,17 @@ main(int argc, char** argv)
assume_sba = false;
}
if (reduction_iterated_dont_care_sim)
{
tm.start("don't care iterated simulation");
temp_dont_care_iterated_sim
= spot::dont_care_iterated_simulations(a, limit_dont_care_sim);
a = temp_dont_care_iterated_sim;
tm.stop("don't care iterated simulation");
assume_sba = false;
}
if (reduction_iterated_sim)
{
tm.start("Reduction w/ iterated simulations");
@ -1170,6 +1213,25 @@ main(int argc, char** argv)
tm.stop("SCC-filter post-sim");
}
if (reduction_dont_care_sim)
{
tm.start("don't care simulation");
temp_dont_care_sim
= spot::dont_care_simulation(a, limit_dont_care_sim);
a = temp_dont_care_sim;
tm.stop("don't care simulation");
if (scc_filter)
{
tm.start("SCC-filter on don't care");
a = spot::scc_filter(a, true);
delete temp_dont_care_sim;
temp_dont_care_sim = a;
tm.stop("SCC-filter on don't care");
}
assume_sba = false;
}
unsigned int n_acc = a->number_of_acceptance_conditions();
if (echeck_inst
&& degeneralize_opt == NoDegen
@ -1673,6 +1735,8 @@ main(int argc, char** argv)
delete temp_dir_sim;
delete temp_rev_sim;
delete temp_iterated_sim;
delete temp_dont_care_sim;
delete temp_dont_care_iterated_sim;
}
else
{