game: reimplement print_aiger
* spot/twaalgos/aiger.cc, spot/twaalgos/aiger.hh: Reimplement print_aiger for speed gain, also heuristics to minimize the number of gates as well as different encoding types have been added. * bin/ltlsynt.cc: Make the new options for print-aiger available. * tests/core/ltlsynt.test: Adjust tests.
This commit is contained in:
philipp
Alexandre Duret-Lutz
parent
f5965966e9
commit
0d43bedacb
5 changed files with 562 additions and 214 deletions
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@ -1,5 +1,5 @@
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// -*- coding: utf-8 -*-
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// Copyright (C) 2017-2019 Laboratoire de Recherche et Développement
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// Copyright (C) 2017-2020 Laboratoire de Recherche et Développement
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// de l'Epita (LRDE).
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//
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// This file is part of Spot, a model checking library.
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@ -21,10 +21,10 @@
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#include <spot/twaalgos/aiger.hh>
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#include <cmath>
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#include <deque>
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#include <map>
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#include <unordered_map>
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#include <vector>
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#include <algorithm>
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#include <cstring>
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#include <spot/twa/twagraph.hh>
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#include <spot/misc/bddlt.hh>
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@ -47,13 +47,16 @@ namespace spot
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class aig
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{
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private:
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unsigned num_inputs_;
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unsigned max_var_;
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std::map<unsigned, std::pair<unsigned, unsigned>> and_gates_;
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unsigned num_inputs_;
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unsigned num_latches_;
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unsigned num_outputs_;
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std::vector<unsigned> latches_;
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std::vector<unsigned> outputs_;
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std::vector<std::string> input_names_;
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std::vector<std::string> output_names_;
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std::vector<std::pair<unsigned, unsigned>> and_gates_;
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// Cache the function computed by each variable as a bdd.
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std::unordered_map<unsigned, bdd> var2bdd_;
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std::unordered_map<bdd, unsigned, bdd_hash> bdd2var_;
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@ -62,8 +65,10 @@ namespace spot
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aig(const std::vector<std::string>& inputs,
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const std::vector<std::string>& outputs,
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unsigned num_latches)
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: num_inputs_(inputs.size()),
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max_var_((inputs.size() + num_latches)*2),
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: max_var_((inputs.size() + num_latches)*2),
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num_inputs_(inputs.size()),
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num_latches_(num_latches),
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num_outputs_(outputs.size()),
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latches_(num_latches),
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outputs_(outputs.size()),
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input_names_(inputs),
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@ -73,38 +78,58 @@ namespace spot
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var2bdd_[1] = bddtrue;
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bdd2var_[bddfalse] = 0;
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var2bdd_[0] = bddfalse;
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bdd2var_.reserve(4 * (num_inputs_ + num_latches_));
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var2bdd_.reserve(4 * (num_inputs_ + num_latches_));
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}
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aig(unsigned num_inputs, unsigned num_latches, unsigned num_outputs)
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: aig(name_vector(num_inputs, "in"), name_vector(num_outputs, "out"),
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num_latches)
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{}
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unsigned input_var(unsigned i, bdd b)
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{
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assert(i < num_inputs_);
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unsigned v = (1 + i) * 2;
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bdd2var_[b] = v;
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var2bdd_[v] = b;
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return v;
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}
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unsigned latch_var(unsigned i, bdd b)
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// register the bdd corresponding the an
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// aig literal
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inline void register_new_lit(unsigned v, const bdd& b)
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{
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assert(!var2bdd_.count(v) || var2bdd_.at(v) == b);
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assert(!bdd2var_.count(b) || bdd2var_.at(b) == v);
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var2bdd_[v] = b;
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bdd2var_[b] = v;
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// Also store negation
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// Do not use aig_not as tests will fail
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var2bdd_[v ^ 1] = !b;
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bdd2var_[!b] = v ^ 1;
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}
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inline unsigned input_var(unsigned i) const
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{
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assert(i < num_inputs_);
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return (1 + i) * 2;
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}
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inline unsigned latch_var(unsigned i)
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{
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assert(i < latches_.size());
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unsigned v = (1 + num_inputs_ + i) * 2;
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bdd2var_[b] = v;
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var2bdd_[v] = b;
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return v;
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return (1 + num_inputs_ + i) * 2;
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}
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inline unsigned gate_var(unsigned i)const
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{
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assert(i < and_gates_.size());
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return (1 + num_inputs_ + num_latches_ + i) * 2;
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}
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void set_output(unsigned i, unsigned v)
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{
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assert(v <= max_var_+1);
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outputs_[i] = v;
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}
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void set_latch(unsigned i, unsigned v)
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{
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assert(v <= max_var_+1);
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latches_[i] = v;
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}
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@ -121,9 +146,8 @@ namespace spot
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unsigned aig_not(unsigned v)
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{
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unsigned not_v = v ^ 1;
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assert(var2bdd_.count(v));
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var2bdd_[not_v] = !(var2bdd_[v]);
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bdd2var_[var2bdd_[not_v]] = not_v;
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assert(var2bdd_.count(v)
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&& var2bdd_.count(not_v));
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return not_v;
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}
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@ -136,9 +160,8 @@ namespace spot
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if (it != bdd2var_.end())
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return it->second;
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max_var_ += 2;
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and_gates_[max_var_] = {v1, v2};
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bdd2var_[b] = max_var_;
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var2bdd_[max_var_] = b;
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and_gates_.emplace_back(v1, v2);
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register_new_lit(max_var_, b);
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return max_var_;
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}
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@ -150,12 +173,20 @@ namespace spot
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return vs[0];
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if (vs.size() == 2)
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return aig_and(vs[0], vs[1]);
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unsigned m = vs.size() / 2;
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unsigned left =
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aig_and(std::vector<unsigned>(vs.begin(), vs.begin() + m));
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unsigned right =
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aig_and(std::vector<unsigned>(vs.begin() + m, vs.end()));
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return aig_and(left, right);
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do
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{
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if (vs.size()&1)
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// Odd size -> make even
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vs.push_back(aig_true());
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// Sort to increase reusage gates
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std::sort(vs.begin(), vs.end());
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// Reduce two by two inplace
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for (unsigned i = 0; i < vs.size()/2; ++i)
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vs[i] = aig_and(vs[2*i], vs[2*i + 1]);
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vs.resize(vs.size()/2);
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}while (vs.size() > 1);
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return vs[0];
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}
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unsigned aig_or(unsigned v1, unsigned v2)
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@ -174,121 +205,227 @@ namespace spot
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unsigned aig_pos(unsigned v)
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{
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return v & ~1;
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}
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void remove_unused()
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{
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// Run a DFS on the gates and latches to collect
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// Run a DFS on the gates to collect
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// all nodes connected to the output.
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std::deque<unsigned> todo;
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std::vector<bool> used(max_var_ / 2 + 1, false);
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std::vector<unsigned> todo;
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std::vector<bool> used(and_gates_.size(), false);
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// The variables are numbered by first enumerating
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// inputs, latches and finally the and-gates
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// v_latch = (1+n_i+i)*2 if latch is in positive form
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// if v/2 < 1+n_i -> v is an input
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// v_gate = (1+n_i+n_l+i)*2 if gate is in positive form
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// if v/2 < 1+n_i_nl -> v is a latch
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auto v2idx = [&](unsigned v)->unsigned
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{
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assert(!(v & 1));
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const unsigned Nlatch_min = 1 + num_inputs_;
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const unsigned Ngate_min = 1 + num_inputs_ + num_latches_;
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// Note: this will at most run twice
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while (true)
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{
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unsigned i = v / 2;
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if (i >= Ngate_min)
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// v is a gate
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return i - Ngate_min;
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else if (i >= Nlatch_min)
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// v is a latch -> get gate
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v = aig_pos(latches_.at(i - Nlatch_min));
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else
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// v is a input -> nothing to do
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return -1U;
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}
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};
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auto mark = [&](unsigned v)
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{
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unsigned pos = aig_pos(v);
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if (!used[pos/2])
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{
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used[pos/2] = 1;
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todo.push_back(pos);
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}
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};
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{
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unsigned idx = v2idx(aig_pos(v));
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if ((idx == -1U) || used[idx])
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return;
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used[idx] = true;
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todo.push_back(idx);
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};
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for (unsigned v : outputs_)
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mark(v);
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while (!todo.empty())
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{
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unsigned v = todo.front();
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todo.pop_front();
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auto it_and = and_gates_.find(v);
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if (it_and != and_gates_.end())
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{
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mark(it_and->second.first);
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mark(it_and->second.second);
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}
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else if (v <= (num_inputs_ + latches_.size()) * 2
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&& v > num_inputs_ * 2)
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{
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mark(latches_[v / 2 - num_inputs_ - 1]);
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}
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unsigned idx = todo.back();
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todo.pop_back();
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mark(and_gates_[idx].first);
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mark(and_gates_[idx].second);
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}
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// Erase and_gates that were not seen in the above
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// exploration.
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auto e = and_gates_.end();
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for (auto i = and_gates_.begin(); i != e;)
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// To avoid renumbering all gates, erasure is done
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// by setting both inputs to "false"
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for (unsigned idx = 0; idx < used.size(); ++idx)
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if (!used[idx])
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{
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and_gates_[idx].first = 0;
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and_gates_[idx].second = 0;
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}
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}
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// Takes a bdd, computes the corresponding literal
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// using its DNF
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unsigned bdd2DNFvar(const bdd& b,
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const std::unordered_map<unsigned, unsigned>&
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bddvar_to_num)
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{
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std::vector<unsigned> plus_vars;
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std::vector<unsigned> prod_vars(num_inputs_);
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minato_isop cond(b);
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bdd prod;
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while ((prod = cond.next()) != bddfalse)
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{
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if (!used[i->first/2])
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i = and_gates_.erase(i);
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prod_vars.clear();
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// Check if existing
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auto it = bdd2var_.find(prod);
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if (it != bdd2var_.end())
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plus_vars.push_back(it->second);
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else
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++i;
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{
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// Create
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while (prod != bddfalse && prod != bddtrue)
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{
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unsigned v =
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input_var(bddvar_to_num.at(bdd_var(prod)));
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if (bdd_high(prod) == bddfalse)
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{
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v = aig_not(v);
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prod = bdd_low(prod);
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}
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else
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prod = bdd_high(prod);
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prod_vars.push_back(v);
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}
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plus_vars.push_back(aig_and(prod_vars));
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}
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}
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// Done building
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return aig_or(plus_vars);
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}
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// Takes a bdd, computes the corresponding literal
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// using its INF
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unsigned bdd2INFvar(bdd b)
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{
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// F = !v&low | v&high
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// De-morgan
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// !(!v&low | v&high) = !(!v&low) & !(v&high)
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// !v&low | v&high = !(!(!v&low) & !(v&high))
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auto b_it = bdd2var_.find(b);
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if (b_it != bdd2var_.end())
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return b_it->second;
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unsigned v_var = bdd2var_.at(bdd_ithvar(bdd_var(b)));
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bdd b_branch[2] = {bdd_low(b), bdd_high(b)};
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unsigned b_branch_var[2];
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for (unsigned i: {0, 1})
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{
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auto b_branch_it = bdd2var_.find(b_branch[i]);
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if (b_branch_it == bdd2var_.end())
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b_branch_var[i] = bdd2INFvar(b_branch[i]);
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else
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b_branch_var[i] = b_branch_it->second;
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}
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unsigned r = aig_not(aig_and(v_var, b_branch_var[1]));
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unsigned l = aig_not(aig_and(aig_not(v_var), b_branch_var[0]));
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return aig_not(aig_and(l, r));
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}
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void
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print(std::ostream& os) const
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{
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// Writing gates to formatted buffer speed-ups output
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// as it avoids "<<" calls
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// vars are unsigned -> 10 digits at most
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char gate_buffer[3*10+5];
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auto write_gate = [&](unsigned o, unsigned i0, unsigned i1)
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{
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std::sprintf(gate_buffer, "%u %u %u\n", o, i0, i1);
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os << gate_buffer;
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};
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// Count active gates
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unsigned n_gates=0;
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for (auto& g : and_gates_)
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if ((g.first != 0) && (g.second != 0))
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++n_gates;
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// Note max_var_ is now an upper bound
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os << "aag " << max_var_ / 2
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<< ' ' << num_inputs_
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<< ' ' << latches_.size()
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<< ' ' << outputs_.size()
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<< ' ' << and_gates_.size() << '\n';
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<< ' ' << num_latches_
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<< ' ' << num_outputs_
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<< ' ' << n_gates << '\n';
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for (unsigned i = 0; i < num_inputs_; ++i)
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os << (1 + i) * 2 << '\n';
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for (unsigned i = 0; i < latches_.size(); ++i)
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for (unsigned i = 0; i < num_latches_; ++i)
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os << (1 + num_inputs_ + i) * 2 << ' ' << latches_[i] << '\n';
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for (unsigned i = 0; i < outputs_.size(); ++i)
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os << outputs_[i] << '\n';
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for (auto& p : and_gates_)
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os << p.first
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<< ' ' << p.second.first
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<< ' ' << p.second.second << '\n';
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for (unsigned i=0; i<and_gates_.size(); ++i)
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if ((and_gates_[i].first != 0) && (and_gates_[i].second != 0))
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write_gate(gate_var(i), and_gates_[i].first, and_gates_[i].second);
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for (unsigned i = 0; i < num_inputs_; ++i)
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os << 'i' << i << ' ' << input_names_[i] << '\n';
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for (unsigned i = 0; i < outputs_.size(); ++i)
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os << 'o' << i << ' ' << output_names_[i] << '\n';
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}
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};
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static std::vector<bool>
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state_to_vec(unsigned s, unsigned size)
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static void
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state_to_vec(std::vector<bool>& v, unsigned s)
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{
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std::vector<bool> v(size);
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for (unsigned i = 0; i < size; ++i)
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for (unsigned i = 0; i < v.size(); ++i)
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{
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v[i] = s & 1;
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s >>= 1;
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}
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return v;
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};
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}
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static std::vector<bool>
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output_to_vec(bdd b,
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const std::unordered_map<unsigned, unsigned>& bddvar_to_outputnum)
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static void
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output_to_vec(std::vector<bool>& v, bdd b,
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const std::unordered_map<unsigned, unsigned>&
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bddvar_to_outputnum)
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{
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std::vector<bool> v(bddvar_to_outputnum.size());
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std::fill(v.begin(), v.end(), false);
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while (b != bddtrue && b != bddfalse)
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{
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unsigned i = bddvar_to_outputnum.at(bdd_var(b));
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v[i] = (bdd_low(b) == bddfalse);
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if (v[i])
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b = bdd_high(b);
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else
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b = bdd_low(b);
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unsigned i = bddvar_to_outputnum.at(bdd_var(b));
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v.at(i) = (bdd_low(b) == bddfalse);
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if (v[i])
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b = bdd_high(b);
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else
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b = bdd_low(b);
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}
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return v;
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}
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static bdd
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state_to_bdd(unsigned s, bdd all)
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state_to_bdd(unsigned s, bdd all_latches)
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{
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bdd b = bddtrue;
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unsigned size = bdd_nodecount(all);
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unsigned size = bdd_nodecount(all_latches);
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if (size)
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{
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unsigned st0 = bdd_var(all);
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unsigned st0 = bdd_var(all_latches);
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for (unsigned i = 0; i < size; ++i)
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{
|
||||
b &= (s & 1) ? bdd_ithvar(st0 + i) : bdd_nithvar(st0 + i);
|
||||
b &= (s & 1) ? bdd_ithvar(st0 + i) : bdd_nithvar(st0 + i);
|
||||
s >>= 1;
|
||||
}
|
||||
}
|
||||
|
|
@ -303,28 +440,84 @@ namespace spot
|
|||
return src == init ? 0 : src == 0 ? init : src;
|
||||
}
|
||||
|
||||
// Takes a product and returns the
|
||||
// number of highs
|
||||
inline unsigned count_high(bdd b)
|
||||
{
|
||||
unsigned high=0;
|
||||
while (b != bddtrue)
|
||||
{
|
||||
if (bdd_low(b) == bddfalse)
|
||||
{
|
||||
++high;
|
||||
b = bdd_high(b);
|
||||
}
|
||||
else
|
||||
{
|
||||
assert(bdd_high(b) == bddfalse);
|
||||
b = bdd_low(b);
|
||||
}
|
||||
}
|
||||
return high;
|
||||
}
|
||||
|
||||
// Heuristic to minimize the number of gates
|
||||
// in the resulting aiger
|
||||
// the idea is to take the (valid) output with the
|
||||
// least "highs" for each transition.
|
||||
// Another idea is to chose conditions such that transitions
|
||||
// can share output conditions. Problem this is a combinatorial
|
||||
// problem and suboptimal solutions that can be computed in
|
||||
// reasonable time have proven to be not as good
|
||||
// Stores the outcondition to use in the used_outc vector
|
||||
// for each transition in aut
|
||||
std::vector<bdd> maxlow_outc(const const_twa_graph_ptr& aut,
|
||||
const bdd& all_inputs)
|
||||
{
|
||||
std::vector<bdd> used_outc(aut->num_edges()+1, bddfalse);
|
||||
|
||||
for (const auto &e : aut->edges())
|
||||
{
|
||||
unsigned idx = aut->edge_number(e);
|
||||
assert(e.cond != bddfalse);
|
||||
bdd bout = bdd_exist(e.cond, all_inputs);
|
||||
assert(((bout & bdd_existcomp(e.cond, all_inputs)) == e.cond) &&
|
||||
"Precondition (in) & (out) == cond violated");
|
||||
unsigned n_high=-1u;
|
||||
while (bout != bddfalse)
|
||||
{
|
||||
bdd nextsat = bdd_satone(bout);
|
||||
bout -= nextsat;
|
||||
unsigned next_high = count_high(nextsat);
|
||||
if (next_high<n_high)
|
||||
{
|
||||
n_high = next_high;
|
||||
used_outc[idx] = nextsat;
|
||||
}
|
||||
}
|
||||
assert(used_outc[idx] != bddfalse);
|
||||
}
|
||||
//Done
|
||||
return used_outc;
|
||||
}
|
||||
|
||||
// Transforms an automaton into an AIGER circuit
|
||||
// using irreducible sums-of-products
|
||||
static aig
|
||||
aut_to_aiger(const const_twa_graph_ptr& aut, const bdd& all_outputs)
|
||||
aut_to_aiger(const const_twa_graph_ptr& aut, const bdd& all_outputs,
|
||||
const char* mode)
|
||||
{
|
||||
// The aiger circuit cannot encode the acceptance condition
|
||||
// Test that the acceptance condition is true
|
||||
if (!aut->acc().is_t())
|
||||
throw std::runtime_error("Cannot turn automaton into aiger circuit");
|
||||
|
||||
// Encode state in log2(num_states) latches.
|
||||
// TODO how hard is it to compute the binary log of a binary integer??
|
||||
unsigned log2n = std::ceil(std::log2(aut->num_states()));
|
||||
unsigned st0 = aut->get_dict()->register_anonymous_variables(log2n, aut);
|
||||
bdd all_states = bddtrue;
|
||||
for (unsigned i = 0; i < log2n; ++i)
|
||||
all_states &= bdd_ithvar(st0 + i);
|
||||
|
||||
// get the propositions
|
||||
std::vector<std::string> input_names;
|
||||
std::vector<std::string> output_names;
|
||||
bdd all_inputs = bddtrue;
|
||||
std::unordered_map<unsigned, unsigned> bddvar_to_inputnum;
|
||||
std::unordered_map<unsigned, unsigned> bddvar_to_outputnum;
|
||||
std::vector<bdd> all_inputs_vec;
|
||||
std::unordered_map<unsigned, unsigned> bddvar_to_num;
|
||||
for (const auto& ap : aut->ap())
|
||||
{
|
||||
int bddvar = aut->get_dict()->has_registered_proposition(ap, aut);
|
||||
|
|
@ -332,92 +525,169 @@ namespace spot
|
|||
bdd b = bdd_ithvar(bddvar);
|
||||
if (bdd_implies(all_outputs, b)) // ap is an output AP
|
||||
{
|
||||
bddvar_to_outputnum[bddvar] = output_names.size();
|
||||
bddvar_to_num[bddvar] = output_names.size();
|
||||
output_names.emplace_back(ap.ap_name());
|
||||
}
|
||||
else // ap is an input AP
|
||||
{
|
||||
bddvar_to_inputnum[bddvar] = input_names.size();
|
||||
bddvar_to_num[bddvar] = input_names.size();
|
||||
input_names.emplace_back(ap.ap_name());
|
||||
all_inputs &= b;
|
||||
all_inputs_vec.push_back(b);
|
||||
}
|
||||
}
|
||||
|
||||
unsigned num_outputs = bdd_nodecount(all_outputs);
|
||||
unsigned num_latches = bdd_nodecount(all_states);
|
||||
// Decide on which outcond to use
|
||||
// The edges of the automaton all have the form in&out
|
||||
// due to the unsplit
|
||||
// however we need the edge to be deterministic in out too
|
||||
// So we need determinism and we also want the resulting aiger
|
||||
// to have as few gates as possible
|
||||
std::vector<bdd> used_outc = maxlow_outc(aut, all_inputs);
|
||||
|
||||
// Encode state in log2(num_states) latches.
|
||||
unsigned log2n = std::ceil(std::log2(aut->num_states()));
|
||||
unsigned st0 = aut->get_dict()->register_anonymous_variables(log2n, aut);
|
||||
|
||||
unsigned num_outputs = output_names.size();
|
||||
unsigned init = aut->get_init_state_number();
|
||||
assert(num_outputs == (unsigned) bdd_nodecount(all_outputs));
|
||||
aig circuit(input_names, output_names, log2n);
|
||||
|
||||
aig circuit(input_names, output_names, num_latches);
|
||||
bdd b;
|
||||
|
||||
// Register
|
||||
// latches
|
||||
for (unsigned i = 0; i < log2n; ++i)
|
||||
circuit.register_new_lit(circuit.latch_var(i), bdd_ithvar(st0+i));
|
||||
// inputs
|
||||
for (unsigned i = 0; i < all_inputs_vec.size(); ++i)
|
||||
circuit.register_new_lit(circuit.input_var(i), all_inputs_vec[i]);
|
||||
// Latches and outputs are expressed as a DNF in which each term
|
||||
// represents a transition.
|
||||
// latch[i] (resp. out[i]) represents the i-th latch (resp. output) DNF.
|
||||
std::vector<std::vector<unsigned>> latch(num_latches);
|
||||
std::vector<std::vector<unsigned>> out(num_outputs);
|
||||
for (unsigned s = 0; s < aut->num_states(); ++s)
|
||||
for (auto& e: aut->out(s))
|
||||
{
|
||||
minato_isop cond(e.cond);
|
||||
while ((b = cond.next()) != bddfalse)
|
||||
{
|
||||
bdd input = bdd_existcomp(b, all_inputs);
|
||||
bdd letter_out = bdd_existcomp(b, all_outputs);
|
||||
auto out_vec = output_to_vec(letter_out, bddvar_to_outputnum);
|
||||
unsigned dst = encode_init_0(e.dst, init);
|
||||
auto next_state_vec = state_to_vec(dst, log2n);
|
||||
unsigned src = encode_init_0(s, init);
|
||||
bdd state_bdd = state_to_bdd(src, all_states);
|
||||
std::vector<unsigned> prod;
|
||||
while (input != bddfalse && input != bddtrue)
|
||||
{
|
||||
unsigned v =
|
||||
circuit.input_var(bddvar_to_inputnum[bdd_var(input)],
|
||||
bdd_ithvar(bdd_var(input)));
|
||||
if (bdd_high(input) == bddfalse)
|
||||
{
|
||||
v = circuit.aig_not(v);
|
||||
input = bdd_low(input);
|
||||
}
|
||||
else
|
||||
input = bdd_high(input);
|
||||
prod.push_back(v);
|
||||
}
|
||||
|
||||
while (state_bdd != bddfalse && state_bdd != bddtrue)
|
||||
{
|
||||
unsigned v =
|
||||
circuit.latch_var(bdd_var(state_bdd) - st0,
|
||||
bdd_ithvar(bdd_var(state_bdd)));
|
||||
if (bdd_high(state_bdd) == bddfalse)
|
||||
{
|
||||
v = circuit.aig_not(v);
|
||||
state_bdd = bdd_low(state_bdd);
|
||||
}
|
||||
else
|
||||
state_bdd = bdd_high(state_bdd);
|
||||
prod.push_back(v);
|
||||
}
|
||||
unsigned t = circuit.aig_and(prod);
|
||||
for (unsigned i = 0; i < next_state_vec.size(); ++i)
|
||||
if (next_state_vec[i])
|
||||
latch[i].push_back(t);
|
||||
for (unsigned i = 0; i < num_outputs; ++i)
|
||||
if (out_vec[i])
|
||||
out[i].push_back(t);
|
||||
}
|
||||
}
|
||||
for (unsigned i = 0; i < num_latches; ++i)
|
||||
circuit.set_latch(i, circuit.aig_or(latch[i]));
|
||||
for (unsigned i = 0; i < num_outputs; ++i)
|
||||
circuit.set_output(i, circuit.aig_or(out[i]));
|
||||
circuit.remove_unused();
|
||||
std::vector<bool> out_vec(output_names.size());
|
||||
std::vector<bool> next_state_vec(log2n);
|
||||
if (strcasecmp(mode, "ISOP") == 0)
|
||||
{
|
||||
std::vector<std::vector<unsigned>> latch(log2n);
|
||||
std::vector<std::vector<unsigned>> out(num_outputs);
|
||||
// Keep track of bdd that were already transformed into a gate
|
||||
std::unordered_map<bdd, unsigned, bdd_hash> incond_map;
|
||||
std::vector<unsigned> prod_state(log2n);
|
||||
for (unsigned s = 0; s < aut->num_states(); ++s)
|
||||
{
|
||||
unsigned src = encode_init_0(s, init);
|
||||
prod_state.clear();
|
||||
unsigned src2 = src;
|
||||
for (unsigned i = 0; i < log2n; ++i)
|
||||
{
|
||||
unsigned v = circuit.latch_var(i);
|
||||
prod_state.push_back(src2 & 1 ? v : circuit.aig_not(v));
|
||||
src2 >>= 1;
|
||||
}
|
||||
assert(src2 <= 1);
|
||||
unsigned state_var = circuit.aig_and(prod_state);
|
||||
// Done state var
|
||||
|
||||
for (auto &e: aut->out(s))
|
||||
{
|
||||
unsigned e_idx = aut->edge_number(e);
|
||||
// Same outcond for all ins
|
||||
const bdd &letter_out = used_outc[e_idx];
|
||||
output_to_vec(out_vec, letter_out, bddvar_to_num);
|
||||
|
||||
unsigned dst = encode_init_0(e.dst, init);
|
||||
state_to_vec(next_state_vec, dst);
|
||||
|
||||
// Get the isops over the input condition
|
||||
// Each isop only contains variables from in
|
||||
// -> directly compute the corresponding
|
||||
// variable and and-gate
|
||||
bdd incond = bdd_exist(e.cond, all_outputs);
|
||||
auto incond_var_it = incond_map.find(incond);
|
||||
if (incond_var_it == incond_map.end())
|
||||
// The incond and its isops have not yet been calculated
|
||||
{
|
||||
bool inserted;
|
||||
unsigned var = circuit.bdd2DNFvar(incond, bddvar_to_num);
|
||||
std::tie(incond_var_it, inserted) =
|
||||
incond_map.insert(std::make_pair(incond, var));
|
||||
assert(inserted && incond_var_it->second == var);
|
||||
}
|
||||
|
||||
// AND with state
|
||||
unsigned t =
|
||||
circuit.aig_and(state_var, incond_var_it->second);
|
||||
// Set in latches/outs having "high"
|
||||
for (unsigned i = 0; i < log2n; ++i)
|
||||
if (next_state_vec[i])
|
||||
latch[i].push_back(t);
|
||||
for (unsigned i = 0; i < num_outputs; ++i)
|
||||
if (out_vec[i])
|
||||
out[i].push_back(t);
|
||||
} // edge
|
||||
} // state
|
||||
|
||||
for (unsigned i = 0; i < log2n; ++i)
|
||||
circuit.set_latch(i, circuit.aig_or(latch[i]));
|
||||
for (unsigned i = 0; i < num_outputs; ++i)
|
||||
circuit.set_output(i, circuit.aig_or(out[i]));
|
||||
circuit.remove_unused();
|
||||
}
|
||||
else if (strcasecmp(mode, "ITE") == 0)
|
||||
{
|
||||
std::vector<bdd> latch(log2n, bddfalse);
|
||||
std::vector<bdd> out(num_outputs, bddfalse);
|
||||
bdd all_latches = bddtrue;
|
||||
for (unsigned i = 0; i < log2n; ++i)
|
||||
all_latches &= bdd_ithvar(st0 + i);
|
||||
|
||||
for (unsigned s = 0; s < aut->num_states(); ++s)
|
||||
{
|
||||
// Convert state to bdd
|
||||
unsigned src = encode_init_0(s, init);
|
||||
bdd src_bdd = state_to_bdd(src, all_latches);
|
||||
|
||||
for (const auto& e : aut->out(src))
|
||||
{
|
||||
unsigned dst = encode_init_0(e.dst, init);
|
||||
state_to_vec(next_state_vec, dst);
|
||||
// edges have the form
|
||||
// f(ins) & f(outs)
|
||||
// one specific truth assignment has been selected above
|
||||
// and stored in used_outc
|
||||
output_to_vec(out_vec, used_outc[aut->edge_number(e)],
|
||||
bddvar_to_num);
|
||||
// The condition that joins in_cond and src
|
||||
bdd tot_cond = src_bdd & bdd_exist(e.cond, all_outputs);
|
||||
|
||||
// Add to existing cond
|
||||
for (unsigned i = 0; i < log2n; ++i)
|
||||
if (next_state_vec[i])
|
||||
latch[i] |= tot_cond;
|
||||
for (unsigned i = 0; i < num_outputs; ++i)
|
||||
if (out_vec[i])
|
||||
out[i] |= tot_cond;
|
||||
} // e
|
||||
} // src
|
||||
// Create the vars
|
||||
for (unsigned i = 0; i < num_outputs; ++i)
|
||||
circuit.set_output(i, circuit.bdd2INFvar(out[i]));
|
||||
for (unsigned i = 0; i < log2n; ++i)
|
||||
circuit.set_latch(i, circuit.bdd2INFvar(latch[i]));
|
||||
}
|
||||
else
|
||||
{
|
||||
throw std::runtime_error
|
||||
("print_aiger(): mode must be \"ISOP\" or \"ITE\"");
|
||||
}
|
||||
|
||||
return circuit;
|
||||
}
|
||||
} // aut_to_aiger_isop
|
||||
}
|
||||
|
||||
std::ostream&
|
||||
print_aiger(std::ostream& os, const const_twa_ptr& aut)
|
||||
print_aiger(std::ostream& os, const const_twa_ptr& aut, const char* mode)
|
||||
{
|
||||
auto a = down_cast<const_twa_graph_ptr>(aut);
|
||||
if (!a)
|
||||
|
|
@ -425,7 +695,8 @@ namespace spot
|
|||
|
||||
bdd* all_outputs = aut->get_named_prop<bdd>("synthesis-outputs");
|
||||
|
||||
aig circuit = aut_to_aiger(a, all_outputs ? *all_outputs : bdd(bddfalse));
|
||||
aig circuit =
|
||||
aut_to_aiger(a, all_outputs ? *all_outputs : bdd(bddfalse), mode);
|
||||
circuit.print(os);
|
||||
return os;
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue