ltlsynt: allow regular expressions in --ins/--outs
* bin/ltlsynt.cc: Implement this. * doc/org/ltlsynt.org, NEWS: Adjust documentation. * tests/core/ltlsynt.test: Add test cases.
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Alexandre Duret-Lutz
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4 changed files with 227 additions and 117 deletions
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@ -22,12 +22,15 @@ specifically as Mealy machines). In the automaton representing the
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controller, the acceptance condition is irrelevant and trivially true.
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=ltlsynt= has three mandatory options:
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- =--ins=: a comma-separated list of input atomic propositions;
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- =--outs=: a comma-separated list of output atomic propositions;
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- =--ins=: a comma-separated list of input atomic propositions, or input regexes enclosed in slashes;
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- =--outs=: a comma-separated list of output atomic propositions, or output regexes enclosed in slashes;
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- =--formula= or =--file=: a specification in LTL or PSL.
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One of =--ins= or =--outs= may be omitted, as any atomic proposition not listed
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as input can be assumed to be output and vice versa.
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One of =--ins= or =--outs= may be omitted, as any atomic proposition
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not listed as input can be assumed to be output and vice versa. If
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both are omitted, =ltlsynts= will assume ~--ins=/^[iI]/~ and
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~--outs=/^[oO]/~, i.e., atomic propositions will be classified as
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input or output based on their first letter.
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The following example illustrates the synthesis of a controller
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ensuring that input =i1= and =i2= are both true initially if and only
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@ -36,7 +39,7 @@ Note that this is an equivalence, not an implication.
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#+NAME: example
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#+BEGIN_SRC sh :exports both
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ltlsynt --ins=i1,i2 -f '(i1 & i2) <-> F(o1 & X(!o1))'
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ltlsynt -f '(i1 & i2) <-> F(o1 & X(!o1))'
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#+END_SRC
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#+RESULTS: example
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@ -55,24 +58,27 @@ State: 0
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[0&1&2] 1
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[!0&2 | !1&2] 2
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State: 1
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[!2] 0
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[!2] 1
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State: 2
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[2] 2
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--END--
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#+end_example
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The output is composed of two parts:
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- The first one is a single line =REALIZABLE= or =UNREALIZABLE=; the presence of this
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line, required by the [[http://http://www.syntcomp.org/][SyntComp competition]], can be disabled with option =--hide-status=.
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- The second one, only present in the =REALIZABLE= case, is an automaton describing the controller.
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- The first part is a single line stating =REALIZABLE= or
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=UNREALIZABLE=; the presence of this line, required by the [[http://http://www.syntcomp.org/][SyntComp
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competition]], can be disabled with option =--hide-status=.
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- The second part, only present in the =REALIZABLE= case, is an
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automaton describing the controller.
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The controller contains the line =controllable-AP: 2=, which means that this automaton
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should be interpreted as a Mealy machine where =o0= is part of the output.
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Using the =--dot= option, makes it easier to visualize this machine.
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The controller contains the line =controllable-AP: 2=, which means
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that this automaton should be interpreted as a Mealy machine where
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=o0= is part of the output. Using the =--dot= option, makes it easier
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to visualize this machine.
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#+NAME: exampledot
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#+BEGIN_SRC sh :exports code
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ltlsynt --ins=i1,i2 -f '(i1 & i2) <-> F(o1 & X(!o1))' --hide-status --dot
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ltlsynt -f '(i1 & i2) <-> F(o1 & X(!o1))' --hide-status --dot
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#+END_SRC
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#+BEGIN_SRC dot :file ltlsyntex.svg :var txt=exampledot :exports results
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@ -99,28 +105,32 @@ flag. This is the output format required for the [[http://syntcomp.org/][SYNTCOM
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#+NAME: exampleaig
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#+BEGIN_SRC sh :exports both
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ltlsynt --ins=i1,i2 -f '(i1 & i2) <-> F(o1 & X(!o1))' --aiger
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ltlsynt -f '(i1 & i2) <-> F(o1 & X(!o1))' --aiger
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#+END_SRC
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#+RESULTS: exampleaig
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#+begin_example
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REALIZABLE
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aag 14 2 2 1 10
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aag 18 2 2 1 14
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2
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4
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6 14
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8 29
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6 23
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8 37
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7
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10 7 9
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12 4 10
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14 2 12
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16 7 8
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18 4 16
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20 5 7
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22 21 19
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24 2 23
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26 3 7
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28 27 25
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10 6 9
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12 4 9
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14 5 10
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16 13 15
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18 2 17
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20 3 10
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22 19 21
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24 7 8
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26 4 24
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28 5 7
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30 27 29
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32 2 31
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34 3 7
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36 33 35
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i0 i1
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i1 i2
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o0 o1
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@ -132,7 +142,7 @@ the controller:
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#+NAME: exampleaigdot
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#+BEGIN_SRC sh :exports code
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ltlsynt --ins=i1,i2 -f '(i1 & i2) <-> F(o1 & X(!o1))' --hide-status --aiger --dot
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ltlsynt -f '(i1 & i2) <-> F(o1 & X(!o1))' --hide-status --aiger --dot
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#+END_SRC
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#+BEGIN_SRC dot :file ltlsyntexaig.svg :var txt=exampleaigdot :exports results
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@ -147,7 +157,7 @@ circles represent inversions (or negations), colored triangles are
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used to represent input signals (at the bottom) and output signals (at
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the top), and finally rectangles represent latches. A latch is a one
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bit register that delays the signal by one step. Initially, all
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latches are assumed to contain =false=, and them emit their value from
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latches are assumed to contain =false=, and they emit their value from
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the =L0_out= and =L1_out= rectangles at the bottom. Their input value,
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to be emitted at the next step, is received via the =L0_in= and =L1_in=
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boxes at the top. In =ltlsynt='s encoding, the set of latches is used
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@ -172,8 +182,9 @@ be synthesized using =syfco= and =ltlsynt=:
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ltlsynt --tlsf FILE
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#+END_SRC
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The above =--tlsf= option will call =syfco= to perform the conversion
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and extract output signals, as if you had used:
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The above =--tlsf= option will call =syfco= (which must be on your
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=$PATH=) to perform the conversion and extract output signals, as if
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you had used:
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#+BEGIN_SRC sh :export code
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LTL=$(syfco -f ltlxba -m fully FILE)
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@ -181,6 +192,7 @@ OUT=$(syfco --print-output-signals FILE)
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ltlsynt --formula="$LTL" --outs="$OUT"
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#+END_SRC
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* Internal details
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The tool reduces the synthesis problem to a parity game, and solves the parity
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@ -237,13 +249,13 @@ be tried by separating them using commas. For instance
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You can also ask =ltlsynt= to print to obtained parity game into
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[[https://github.com/tcsprojects/pgsolver][PGSolver]] format, with the flag =--print-pg=, or in the HOA format,
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using =--print-game-hoa=. These flag deactivate the resolution of the
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using =--print-game-hoa=. These flags deactivate the resolution of the
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parity game. Note that if any of those flag is used with =--dot=, the game
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will be printed in the Dot format instead:
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#+NAME: examplegamedot
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#+BEGIN_SRC sh :exports code
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ltlsynt --ins=i1,i2 -f '(i1 & i2) <-> F(o1 & X(!o1))' --print-game-hoa --dot
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ltlsynt -f '(i1 & i2) <-> F(o1 & X(!o1))' --print-game-hoa --dot
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#+END_SRC
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#+BEGIN_SRC dot :file ltlsyntexgame.svg :var txt=examplegamedot :exports results
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$txt
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