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fix warnings from clang-15

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* spot/twa/acc.cc (acc_cond::acc_code::symmetries): Fix weird loop.
* spot/twaalgos/aiger.cc (aig::circ_step): Replace & by &&.
This commit is contained in:
Alexandre Duret-Lutz 2022-05-17 11:43:55 +02:00
parent 5dab2ede41
commit 3a234e24ae
2 changed files with 4 additions and 4 deletions
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4
spot/twa/acc.cc
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@ -1,5 +1,5 @@
// -*- coding: utf-8 -*-
// Copyright (C) 2015-2021 Laboratoire de Recherche et Développement
// Copyright (C) 2015-2022 Laboratoire de Recherche et Développement
// de l'Epita.
//
// This file is part of Spot, a model checking library.
@ -1029,7 +1029,7 @@ namespace spot
int base = ba.allocate_variables(umax+2);
assert(base == 0);
std::vector<bdd> r;
for (unsigned i = 0; r.size() < umax; ++i)
while (r.size() < umax)
r.emplace_back(bdd_ithvar(base++));
bdd bddcode = to_bdd(&r[0]);
bdd tmp;

4
spot/twaalgos/aiger.cc
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@ -1,5 +1,5 @@
// -*- coding: utf-8 -*-
// Copyright (C) 2017-2021 Laboratoire de Recherche et Développement
// Copyright (C) 2017-2022 Laboratoire de Recherche et Développement
// de l'Epita (LRDE).
//
// This file is part of Spot, a model checking library.
@ -1398,7 +1398,7 @@ namespace spot
{
unsigned var_g = gate_var(i);
state_[var_g] = state_[and_gates_[i].first]
& state_[and_gates_[i].second];
&& state_[and_gates_[i].second];
state_[aig_not(var_g)] = !state_[var_g];
}
// Update latches