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ltlsynt: display ACD instead of LAR when needed

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* spot/twaalgos/synthesis.cc: here
* tests/core/ltlsynt.test: add test
This commit is contained in:
Florian Renkin 2022-04-12 11:19:49 +02:00
parent 5f43c9bfce
commit 55aac8e107
2 changed files with 28 additions and 1 deletions
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spot/twaalgos/synthesis.cc
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@ -1022,7 +1022,8 @@ namespace spot
if (bv)
bv->paritize_time += sw.stop();
if (vs)
*vs << "LAR construction done in " << bv->paritize_time
*vs << (gi.s == algo::ACD ? "ACD" : "LAR")
<< " construction done in " << bv->paritize_time
<< " seconds\nDPA has "
<< dpa->num_states() << " states, "
<< dpa->num_sets() << " colors\n";