ltlsynt: improve documentation
This addresses a few points from #479. * doc/org/ltlsynt.tex: New file. * doc/Makefile.am: Add it. * doc/org/ltlsynt.org: Show the architecture, and mention more options. * bin/spot-x.cc: Document ltlsynt's -x options. * bin/ltlsynt.cc: Fix default value of --aiger, and typo in its documentation.
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5 changed files with 229 additions and 20 deletions
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@ -91,7 +91,7 @@ static const argp_option options[] =
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"\"isop\" for irreducible sum of producs; "
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"\"both\" tries both encodings and keeps the smaller one. "
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"The other options further "
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"refine the encoding, see aiger:::encode_bdd.", 0},
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"refine the encoding, see aiger::encode_bdd.", 0},
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{ "verbose", OPT_VERBOSE, nullptr, 0,
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"verbose mode", -1 },
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{ "verify", OPT_VERIFY, nullptr, 0,
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@ -594,7 +594,7 @@ parse_opt(int key, char *arg, struct argp_state *)
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opt_print_hoa_args = arg;
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break;
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case OPT_PRINT_AIGER:
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opt_print_aiger = arg ? arg : "INF";
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opt_print_aiger = arg ? arg : "ite";
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break;
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case OPT_REAL:
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opt_real = true;
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@ -237,6 +237,20 @@ sets. By default this is only enabled when options -B or -S are used.") },
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"Chose which simulation based reduction to use: 1 force the \
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signature-based BDD implementation, 2 force matrix-based and 0, the default, \
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is a heristic wich choose which implementation to use.") },
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{ nullptr, 0, nullptr, 0, "Synthesis options:", 0 },
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{ DOC("specification-decomposition",
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"Set to 0 to disable specification decomposition. Default is 1.") },
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{ DOC("minimization-level",
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"Specify how AIGER circuits should be simplified. "
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"(0) no simplification, "
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"(1) bisimulation-based reduction, "
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"(2) simplification using language inclusion and output assignments, "
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"(3) exact minimization using a SAT solver, "
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"(4) bisimulation-based reduction before exact minimization via "
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"SAT solver, "
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"(5) simplification using output assignments before exact "
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"minimization via SAT solver. "
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"The default value is 1.") },
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{ nullptr, 0, nullptr, 0, nullptr, 0 }
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};
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