ltlsynt: improve documentation
This addresses a few points from #479. * doc/org/ltlsynt.tex: New file. * doc/Makefile.am: Add it. * doc/org/ltlsynt.org: Show the architecture, and mention more options. * bin/spot-x.cc: Document ltlsynt's -x options. * bin/ltlsynt.cc: Fix default value of --aiger, and typo in its documentation.
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5 changed files with 229 additions and 20 deletions
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@ -1,5 +1,5 @@
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## -*- coding: utf-8 -*-
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## Copyright (C) 2010-2011, 2013-2020 Laboratoire de Recherche et
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## Copyright (C) 2010-2011, 2013-2021 Laboratoire de Recherche et
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## Développement de l'Epita (LRDE).
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## Copyright (C) 2003-2005 Laboratoire d'Informatique de Paris 6
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## (LIP6), département Systèmes Répartis Coopératifs (SRC), Université
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@ -103,6 +103,7 @@ ORG_FILES = \
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org/ltlfilt.org \
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org/ltlgrind.org \
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org/ltlsynt.org \
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org/ltlsynt.tex \
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org/oaut.org \
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org/randaut.org \
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org/randltl.org \
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@ -136,6 +137,7 @@ ORG_FILES = \
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PICTURES_EXTRA = \
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$(srcdir)/org/arch.svg \
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$(srcdir)/org/hierarchy.svg \
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$(srcdir)/org/ltlsynt.svg \
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$(srcdir)/org/satmin.svg
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$(srcdir)/org/satmin.svg: org/satmin.tex
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@ -156,6 +158,12 @@ $(srcdir)/org/hierarchy.svg: org/hierarchy.tex
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pdf2svg hierarchy.pdf hierarchy.svg && \
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rm -f hierarchy.pdf hierarchy.aux hierarchy.log
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$(srcdir)/org/ltlsynt.svg: org/ltlsynt.tex
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cd $(srcdir)/org && \
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pdflatex ltlsynt.tex && \
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pdf2svg ltlsynt.pdf ltlsynt.svg && \
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rm -f ltlsynt.pdf ltlsynt.aux ltlsynt.log
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$(srcdir)/org-stamp: $(ORG_FILES) $(configure_ac)
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$(MAKE) org && touch $@
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@ -11,11 +11,16 @@ This tool synthesizes controllers from LTL/PSL formulas.
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Consider a set $I$ of /input/ atomic propositions, a set $O$ of output atomic
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propositions, and a PSL formula \phi over the propositions in $I \cup O$. A
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=controller= realizing \phi is a function $c: 2^{I \cup O} \times 2^I \mapsto
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=controller= realizing \phi is a function $c: (2^{I})^\star \times 2^I \mapsto
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2^O$ such that, for every \omega-word $(u_i)_{i \in N} \in (2^I)^\omega$ over
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the input propositions, the word $(u_i \cup c(u_0 \dots u_{i-1}, u_i))_{i \in
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N}$ satisfies \phi.
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If a controller exists, then one with finite memory exists. Such controllers
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are easily represented as automata (or more specifically as I/O automata or
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transducers). In the automaton representing the controller, the acceptance
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condition is irrelevant and trivially true.
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=ltlsynt= has three mandatory options:
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- =--ins=: a comma-separated list of input atomic propositions;
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- =--outs=: a comma-separated list of output atomic propositions;
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@ -27,23 +32,25 @@ as input can be assumed to be an output and vice-versa.
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The following example illustrates the synthesis of a controller acting as an
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=AND= gate. We have two inputs =a= and =b= and one output =c=, and we want =c=
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to always be the =AND= of the two inputs:
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#+NAME: example
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#+BEGIN_SRC sh :exports both
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ltlsynt --ins=a,b -f 'G (a & b <=> c)'
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#+END_SRC
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#+RESULTS:
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#+RESULTS: example
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#+begin_example
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REALIZABLE
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HOA: v1
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States: 1
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Start: 0
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AP: 3 "b" "c" "a"
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AP: 3 "a" "b" "c"
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acc-name: all
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Acceptance: 0 t
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properties: trans-labels explicit-labels state-acc deterministic
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--BODY--
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State: 0
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[!0&!1 | !1&!2] 0
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[!0&!2 | !1&!2] 0
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[0&1&2] 0
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--END--
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#+end_example
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@ -54,10 +61,22 @@ The output is composed of two parts:
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In this example, the controller has a single
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state, with two loops labeled by =a & b & c= and =(!a | !b) & !c=.
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If a controller exists, then one with finite memory exists. Such controllers
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are easily represented as automata (or more specifically as I/O automata or
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transducers). In the automaton representing the controller, the acceptance
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condition is irrelevant and trivially true.
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#+NAME: exampledot
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#+BEGIN_SRC sh :exports none :noweb yes
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sed 1d <<EOF | autfilt --dot=.A
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<<example()>>
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EOF
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#+END_SRC
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#+BEGIN_SRC dot :file ltlsyntex.svg :var txt=exampledot :exports results
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$txt
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#+END_SRC
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#+RESULTS:
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[[file:ltlsyntex.svg]]
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The label =a & b & c= should be understood as: "if the input is =a&b=,
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the output should be =c=".
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The following example illustrates the case of an unrealizable specification. As
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=a= is an input proposition, there is no way to guarantee that it will
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@ -70,7 +89,6 @@ ltlsynt --ins=a -f 'F a'
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#+RESULTS:
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: UNREALIZABLE
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By default, the controller is output in HOA format, but it can be
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output as an [[http://fmv.jku.at/aiger/][AIGER]] circuit thanks to the =--aiger= flag. This is the
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output format required for the [[http://syntcomp.org/][SYNTCOMP]] competition.
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@ -96,18 +114,74 @@ OUT=$(syfco FILE --print-output-signals)
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ltlsynt --formula="$LTL" --ins="$IN" --outs="$OUT"
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#+END_SRC
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* Algorithm
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* Internal details
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The tool reduces the synthesis problem to a parity game, and solves the parity
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game using Zielonka's recursive algorithm. The full reduction from LTL to
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parity game is described in the following paper:
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- *Reactive Synthesis from LTL Specification with Spot*, /Thibaud Michaud/,
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/Maximilien Colange/. In Proc. of SYNT@CAV'18. to appear.
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game using Zielonka's recursive algorithm. The process can be pictured as follows.
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[[file:ltlsynt.svg]]
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LTL decomposition is described by [[https://arxiv.org/abs/2103.08459][Finkbeiner, Geier, and Passing]], and
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can be disabled by passing option =-x specification-decomposition=0=.
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The idea is to split the specification into multiple smaller
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constraints on disjoint subsets of the output values, solve those
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constraints separately, and then combine them while encoding the AIGER
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circuit.
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The ad hoc construction on the top is just a shortcut for some type of
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constraints that can be solved directly by converting the constraint
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into a DBA.
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Otherwise, conversion to parity game (represented by the blue zone) is
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done using one of several algorithms specified by the =--algo= option.
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The game is then solved, producing a strategy if the game is realizable.
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If an =ltlsynt= is in =--realizability= mode, the process stops here
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In =--aiger= mode, the strategy is first simplified. How this is done
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is controled by option =-x minimize-level=N=. See the [[./man/spot-x.7.html][=spot-x=]](7)
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manpage for details.
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Finally, the strategy is encoded into [[http://fmv.jku.at/aiger/][AIGER]]. The =--aiger= option can
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take an argument to specify a type of encoding to use: by default
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it is =ite= for if-then-else, because it follows the structure of BDD
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used to encode the conditions in the strategy. An alternative encoding
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is =isop= where condition are first put into irredundant-sum-of-product,
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or =both= if both encodings should be tried. Additionally, these optiosn
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can accept the suffix =+ud= (use dual) to attempt to encode each condition
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and its negation and keep the smallest one, =+dc= (don't care) to take
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advantage of /don't care/ values in the output, and one of =+sub0=,
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=+sub1=, or =+sub2= to test various grouping of variables in the encoding.
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Multiple encodings can be tried by separating them using commas.
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For instance =--aiger=isop,isop+dc,isop+ud= will try three different encodings.
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* Other useful options
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You can also ask =ltlsynt= to print to obtained parity game into
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[[https://github.com/tcsprojects/pgsolver][PGSolver]] format, with the flag
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=--print-pg=. Note that this flag deactivates the resolution of the parity
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game, which is to be deferred to one of the solvers from PGSolver.
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[[https://github.com/tcsprojects/pgsolver][PGSolver]] format, with the flag =--print-pg=, or in the HOA format,
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using =--print-game-hoa=. These flag deactivate the resolution of the
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parity game.
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For benchmarking purpose, the =--csv= option can be used to record
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intermediate statistics about the resolution.
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The =--verify= option requests that the produced strategy or aiger
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circuit are compatible with the specification. This is done by
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ensuring that they do not intersect the negation of the specification.
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* References
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The initial reduction from LTL to parity game is described in the
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following paper:
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- *Reactive Synthesis from LTL Specification with Spot*, /Thibaud Michaud/,
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/Maximilien Colange/. Presented in SYNT@CAV'18. ([[https://www.lrde.epita.fr/dload/papers/michaud.18.synt.pdf][pdf]] | [[https://www.lrde.epita.fr/~max/bibtexbrowser.php?key=michaud.18.synt&bib=perso.bib][bib]])
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Further improvements are described in the following paper:
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- *Improvements to =ltlsynt=*, /Florian Renkin/, /Philipp Schlehuber/,
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/Alexandre Duret-Lutz/, and /Adrien Pommellet/. Presented at the
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SYNT'21 workshop. ([[https://www.lrde.epita.fr/~adl/dl/adl/renkin.21.synt.pdf][pdf]] | [[https://www.lrde.epita.fr/~adl/dl/adl_bib.html#renkin.21.synt][bib]])
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# LocalWords: utf ltlsynt AIGER html args mapsto SRC acc aiger TLSF
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# LocalWords: UNREALIZABLE unrealizable SYNTCOMP realizability Proc
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113
doc/org/ltlsynt.tex
Normal file
113
doc/org/ltlsynt.tex
Normal file
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@ -0,0 +1,113 @@
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\documentclass{standalone}
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\usepackage{tikz}
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\usetikzlibrary{arrows}
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\usetikzlibrary{arrows.meta}
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\usetikzlibrary{bending}
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\usetikzlibrary{shadows}
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\usetikzlibrary{positioning}
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\usetikzlibrary{calc}
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\usetikzlibrary{decorations.text}
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\usetikzlibrary{backgrounds}
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\usepackage[hidelinks]{hyperref}
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\begin{document}
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\scalebox{1.2}{
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\begin{tikzpicture}[thick,font=\sffamily,>={Stealth[round,bend]},
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node distance=4mm and 5mm,
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data/.style={text width=1.3cm,minimum height=2em,align=center,draw,fill=magenta!15},
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wproc/.style={fill=yellow!20,align=center,draw,rounded corners=2mm},
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proc/.style={wproc,text width=1.5cm,minimum height=2em},
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lproc/.style={proc,text width=2cm},
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choice/.style={circle,fill=yellow!20,inner sep=0,minimum size=2mm,draw},
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algoopt/.style={postaction={decorate,decoration={text along path, raise=1mm,text={|\ttfamily\small|#1}}}},
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outopt/.style={postaction={decorate,decoration={text along path, text align=right,raise=1mm,text={|\ttfamily\small|#1}}}},
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]
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\node[proc] (transSD) {translate to NBA};
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\node[proc,right=of transSD] (splitSD) {split I/O};
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\node[lproc,right=of splitSD] (detSD) {determinize to DPA};
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\draw[->] (transSD) edge (splitSD)
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(splitSD) edge (detSD);
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\node[proc,below=of transSD] (transDS) {translate to NBA};
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\node[lproc,right=of transDS] (detDS) {determinize to DPA};
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\node[proc,right=of detDS,xshift=2mm] (splitDS) {split I/O};
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\draw[->] (transDS) edge (detDS)
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(detDS) edge coordinate(middetsplit) (splitDS);
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\node[proc,below=of transDS] (transLARold) {translate to DELA};
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\node[lproc,right=of transLARold] (paritizeLARold) {paritize (pure CAR)};
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\draw[->] (transLARold) edge (paritizeLARold)
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(paritizeLARold) edge (middetsplit |- paritizeLARold);
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\node[proc,below=of transLARold] (transLAR) {translate to DELA};
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\node[lproc,right=of transLAR] (paritizeLAR) {paritize (CAR,IAR,{\tiny ...})};
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\draw[->] (transLAR) edge (paritizeLAR)
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(paritizeLAR) edge (middetsplit |- paritizeLAR);
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\node[proc,below=of transLAR] (transPS) {translate to DPA};
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\draw[rounded corners,->] (transPS) -| (middetsplit);
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\coordinate (choicecenter) at ($(current bounding box.west) - (3.3cm,0)$);
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\path[draw] (choicecenter) node[choice](algoin){}
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+(60:8mm) node[choice](algosd){}
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+(30:8mm) node[choice](algods){}
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+(0:8mm) node[choice](algolarold){}
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+(-30:8mm) node[choice](algolar){}
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+(-60:8mm) node[choice](algops){};
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\draw[->,algoopt={-{}-algo=sd}] (algosd) to[out=60,in=180] (transSD);
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\draw[->,algoopt={-{}-algo=ds}] (algods) to[out=30,in=180] (transDS);
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\draw[->,algoopt={-{}-algo=lar.old}] (algolarold) -- (transLARold);
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\draw[->,algoopt={-{}-algo=lar}] (algolar) to[out=-30,in=180] (transLAR);
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\draw[->,algoopt={-{}-algo=ps}] (algops) to[out=-60,in=180] (transPS);
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\draw[ultra thick] (algoin) -- (algolar.north);
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\node[choice,left=of algoin] (bypassin) {};
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\node[proc,left=of bypassin,yshift=1cm,text width=1.6cm] (decomp) {decompose};
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\node[data,above=of decomp] (input) {LTL input};
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\draw[->] (input) -- (decomp);
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\draw[->] (decomp) to[out=-45,in=180] (bypassin);
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\draw[->,gray] (decomp) to[out=-55,in=180] ($(bypassin.west)+(0,-0.33)$);
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\draw[->,gray] (decomp) to[out=-65,in=180] ($(bypassin.west)+(0,-0.66)$);
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\draw[->,gray] (decomp) to[out=-75,in=180] ($(bypassin.west)+(0,-1)$);
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\draw[->] (bypassin) -- (algoin);
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\node[lproc, right=of detSD, xshift=4mm] (solve) {solve\linebreak parity game};
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\node[below=of solve,choice] (reachoice) {};
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\node[below right=of reachoice,choice,xshift=-3mm,yshift=-1mm] (realize) {};
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\node[below left=of reachoice,choice,xshift=3mm,yshift=-1mm] (aiger) {};
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\draw[ultra thick] (reachoice) -- (realize.west);
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\draw[->] (solve) -- (reachoice);
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\node[data] (yesno) at ($(transPS -| realize)+(0,-2mm)$) {Y/N output};
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\node[data, text width=1.2cm, left=of yesno] (output) {AIGER output};
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\node[proc, above=of output,yshift=-1mm] (encode) {encode in AIGER};
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\node[proc, above=of encode,yshift=+1mm] (minimize) {simplify\linebreak strategy};
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\draw[->] (detSD) -- coordinate(middetsolve) (solve);
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\draw[rounded corners,->] (splitDS) -| (middetsolve);
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\draw[<-,outopt={-{}-aiger}] (minimize) to[out=90,in=-160] (aiger);
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\draw[->] (minimize) -- (encode);
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\draw[gray,->] ($(encode.north)+(2mm,3mm)$) -- ($(encode.north)+(2mm,0)$);
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\draw[gray,->] ($(encode.north)+(4mm,3mm)$) -- ($(encode.north)+(4mm,0)$);
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\draw[gray,->] ($(encode.north)+(6mm,3mm)$) -- ($(encode.north)+(6mm,0)$);
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\draw[<-,outopt={-{}-realizability~}] (yesno) -- (realize);
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\draw[gray,->] ($(yesno.north)+(2mm,3mm)$) -- ($(yesno.north)+(2mm,0)$);
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\draw[gray,->] ($(yesno.north)+(4mm,3mm)$) -- ($(yesno.north)+(4mm,0)$);
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\draw[gray,->] ($(yesno.north)+(6mm,3mm)$) -- ($(yesno.north)+(6mm,0)$);
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%\draw[->] (solve) -- (encode);
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\draw[->] (encode) -- (output);
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\begin{scope}[on background layer,overlay]
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\fill[cyan!20,rounded corners=5mm]
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($(algoin |- transPS.south)+(-.4,-.2)$) |-
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($(detSD.north -| middetsolve)+(.2,.2)$) |-
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($(splitDS.south west)+(.2,-.2)$) |- cycle;
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\end{scope}
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\coordinate (solveright) at ($(solve.east)+(2mm,0)$);
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\path (bypassin) -- coordinate(medblue) (solveright);
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\node[wproc,above,xshift=-1mm,yshift=4mm] (bypass) at (medblue |- detSD.north) {specialized strategy construction for formulas of the form $\mathsf{G}(b_1) \land (\varphi \leftrightarrow \mathsf{G}\mathsf{F} b_2)$};
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\draw[rounded corners,->] (bypassin) |- (bypass);
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\draw[rounded corners,->] (bypass) -| (solveright) |- (reachoice);
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\end{tikzpicture}}
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\end{document}
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