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bitvect: implement a dynamic bit-vector class.

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* src/misc/bitvect.cc, src/misc/bitvect.hh: New files.
* src/misc/Makefile.am: Add them.
* src/tgbatest/bitvect.cc, src/tgbatest/bitvect.test: New files.
* src/tgbatest/Makefile.am: Add them.
This commit is contained in:
Alexandre Duret-Lutz 2013-07-24 19:21:08 +02:00
parent dfc5ff95e5
commit 5a3b1a9905
6 changed files with 877 additions and 0 deletions
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90
src/tgbatest/bitvect.test Executable file
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@ -0,0 +1,90 @@
#!/bin/sh
# Copyright (C) 2013 Laboratoire de Recherche et Développement
# de l'Epita (LRDE).
#
# This file is part of Spot, a model checking library.
#
# Spot is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
# Spot is distributed in the hope that it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
# License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
. ./defs
set -e
run 0 ../bitvect | tee stderr
cat >expected <<EOF
0_________1_________2_________3_________4_________5_________6_________7_____
0123456789012345678901234567890123456789012345678901234567890123456789012345
v: 000000000000000
v: 000000010010100
0_________1_________2_________3_________4_________5_________6_________7_____
0123456789012345678901234567890123456789012345678901234567890123456789012345
w: 000000010000010000000000000000100000000001
w: 000000000010110000000000000000100000000001
0_________1_________2_________3_________4_________5_________6_________7_____
0123456789012345678901234567890123456789012345678901234567890123456789012345
x: 000000000000000000000000000000000000000000000000000000000000100000000010000
x: 000000000010110000000000000000100000000001000000000000000000100000000010000
w: 000000000010110000000000000000100000000001100010001000100010001000100010
x: 000000000010110000000000000000100000000001000000000000000000000000000010000
x: 111111111111111111111111111111111111111111111111111111111111111111111111111
0_________1_________2_________3_________4_________5_________6_________7_____
0123456789012345678901234567890123456789012345678901234567890123456789012345
w: 0000000000101100000000000000001000000000011000100010001000100010001000101001
y: 00000000001011000000000000000010000000000110001000100010001000100010001
y: 0000000000101100000000000000001000000000011000100010001000100010
y: 00100010100
y: 000000000010110000000000000000100000000001100010001000100010001000100010100
y: 000101100000000000000001000000000011000100010001000100010
y: 00010110000000000000000100000000001100010001000100010001000100010
0_________1_________2_________3_________4_________5_________6_________7_____
0123456789012345678901234567890123456789012345678901234567890123456789012345
0: 110011001100110011001100110011001100110011001100110011001100
1: 110011001100110011001100110011001100110011001100110011001100
2: 001100110011001100110011001100110011001100110011001100110011
3: 001100110011001100110011001100110011001100110011001100110011
4: 110011001100110011001100110011001100110011001100110011001100
5: 110011001100110011001100110011001100110011001100110011001100
6: 001100110011001100110011001100110011001100110011001100110011
7: 001100110011001100110011001100110011001100110011001100110011
8: 110011001100110011001100110011001100110011001100110011001100
9: 110011001100110011001100110011001100110011001100110011001100
0_________1_________2_________3_________4_________5_________6_________7_____
0123456789012345678901234567890123456789012345678901234567890123456789012345
0: 110011001100110011001100110011001100110011001100110011001100
1: 110011001100110011001100110011001100110011001100110011001100
2: 001100110011001100110011001100110011001100110011001100110011
3: 001100110011001100110011001100110011001100110011001100110011
4: 110011001100110011001100110011001100110011001100110011001100110011001100
5: 110011001100110011001100110011001100110011001100110011001100
6: 111111111111111111111111111111111111111111111111111111111111110011001100
7: 001100110011001100110011001100110011001100110011001100110011
8: 001100110011001100110011001100110011001100110011001100110011
9: 110011001100110011001100110011001100110011001100110011001100
Comp: 1011010
EOF
diff expected stderr