aiger: order the inputs of binary AND gates
* spot/twaalgos/aiger.cc: Here. * tests/core/ltlsynt.test: Adjust, and add test case for aiger=optim.
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2 changed files with 21 additions and 17 deletions
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@ -1,5 +1,5 @@
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// -*- coding: utf-8 -*-
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// Copyright (C) 2017-2022 Laboratoire de Recherche et Développement
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// Copyright (C) 2017-2023 Laboratoire de Recherche et Développement
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// de l'Epita (LRDE).
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//
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// This file is part of Spot, a model checking library.
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@ -552,20 +552,20 @@ namespace spot
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assert(var2bdd_.count(v1));
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assert(var2bdd_.count(v2));
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if (v1 != v2)
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{
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bdd b = var2bdd_[v1] & var2bdd_[v2];
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auto [it, inserted] = bdd2var_.try_emplace(b.id(), 0);
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if (!inserted)
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return it->second;
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max_var_ += 2;
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it->second = max_var_;
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and_gates_.emplace_back(v1, v2);
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register_new_lit_(max_var_, b);
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return max_var_;
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}
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else
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return v1;
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if (SPOT_UNLIKELY(v1 > v2))
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std::swap(v1, v2);
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if (SPOT_UNLIKELY(v1 == v2))
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return v1;
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bdd b = var2bdd_[v1] & var2bdd_[v2];
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auto [it, inserted] = bdd2var_.try_emplace(b.id(), 0);
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if (!inserted)
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return it->second;
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max_var_ += 2;
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it->second = max_var_;
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and_gates_.emplace_back(v1, v2);
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register_new_lit_(max_var_, b);
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return max_var_;
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}
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unsigned aig::aig_and(std::vector<unsigned>& vs)
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