ltlsynt: add options --dot and --hide-status
* bin/ltlsynt.cc: Implement these options. * bin/common_aoutput.hh, bin/common_aoutput.cc (automaton_format_opt): Make extern. * NEWS: Mention the new options. * doc/org/ltlsynt.org: Use dot output in documentation. * tests/core/ltlsynt.test: Quick test of the new options.
This commit is contained in:
Alexandre Duret-Lutz
parent
ef0aeed228
commit
c1c874b1a5
6 changed files with 205 additions and 67 deletions
10
NEWS
10
NEWS
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@ -36,6 +36,16 @@ New in spot 2.10.6.dev (not yet released)
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- ltlsynt has a new option --from-pgame that takes a parity game in
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extended HOA format, as used in the Synthesis Competition.
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- ltlsynt has a new option --hide-status to hide the REALIZABLE or
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UNREALIZABLE output expected by SYNTCOMP. (This line is
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superfluous, because the exit status of ltlsynt already indicate
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whether the formula is realizable or not.)
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- ltlsynt has a new option --dot to request GraphViz output instead
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of most output. This works for displaying Mealy machines, games,
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or AIG circuits. See https://spot.lrde.epita.fr/ltlsynt.html for
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examples.
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- genaut learned the --cyclist-trace-nba and --cyclist-proof-dba
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options. Those are used to generate pairs of automata that should
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include each other, and are used to show a regression (in speed)
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@ -1,5 +1,5 @@
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// -*- coding: utf-8 -*-
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// Copyright (C) 2012-2021 Laboratoire de Recherche et Développement
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// Copyright (C) 2012-2022 Laboratoire de Recherche et Développement
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// de l'Epita (LRDE).
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//
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// This file is part of Spot, a model checking library.
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@ -41,7 +41,7 @@
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#include <spot/twaalgos/isdet.hh>
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automaton_format_t automaton_format = Hoa;
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static const char* automaton_format_opt = nullptr;
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const char* automaton_format_opt = nullptr;
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const char* opt_name = nullptr;
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static const char* opt_output = nullptr;
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static const char* stats = "";
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@ -1,5 +1,5 @@
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// -*- coding: utf-8 -*-
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// Copyright (C) 2014-2018, 2020 Laboratoire de Recherche et
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// Copyright (C) 2014-2018, 2020, 2022 Laboratoire de Recherche et
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// Développement de l'Epita (LRDE).
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//
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// This file is part of Spot, a model checking library.
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@ -47,6 +47,7 @@ enum automaton_format_t {
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// The format to use in output_automaton()
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extern automaton_format_t automaton_format;
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extern const char* automaton_format_opt;
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// Set to the argument of --name, else nullptr.
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extern const char* opt_name;
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// Output options
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@ -37,6 +37,7 @@
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#include <spot/twaalgos/aiger.hh>
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#include <spot/twaalgos/game.hh>
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#include <spot/twaalgos/hoa.hh>
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#include <spot/twaalgos/dot.hh>
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#include <spot/twaalgos/minimize.hh>
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#include <spot/twaalgos/mealy_machine.hh>
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#include <spot/twaalgos/product.hh>
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@ -49,7 +50,9 @@ enum
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OPT_BYPASS,
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OPT_CSV,
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OPT_DECOMPOSE,
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OPT_DOT,
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OPT_FROM_PGAME,
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OPT_HIDE,
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OPT_INPUT,
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OPT_OUTPUT,
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OPT_PRINT,
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@ -107,32 +110,41 @@ static const argp_option options[] =
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/**************************************************/
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{ nullptr, 0, nullptr, 0, "Output options:", 20 },
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{ "print-pg", OPT_PRINT, nullptr, 0,
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"print the parity game in the pgsolver format, do not solve it", 0},
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"print the parity game in the pgsolver format, do not solve it", 0 },
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{ "print-game-hoa", OPT_PRINT_HOA, "options", OPTION_ARG_OPTIONAL,
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"print the parity game in the HOA format, do not solve it", 0},
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"print the parity game in the HOA format, do not solve it", 0 },
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{ "realizability", OPT_REAL, nullptr, 0,
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"realizability only, do not compute a winning strategy", 0},
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"realizability only, do not compute a winning strategy", 0 },
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{ "aiger", OPT_PRINT_AIGER, "ite|isop|both[+ud][+dc]"
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"[+sub0|sub1|sub2]", OPTION_ARG_OPTIONAL,
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"prints a winning strategy as an AIGER circuit. The first word "
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"indicates the encoding to used: \"ite\" for "
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"encode the winning strategy as an AIG circuit and print it in AIGER"
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" format. The first word indicates the encoding to used: \"ite\" for "
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"If-Then-Else normal form; "
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"\"isop\" for irreducible sum of producs; "
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"\"isop\" for irreducible sum of products; "
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"\"both\" tries both and keeps the smaller one. "
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"The other options further "
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"refine the encoding, see aiger::encode_bdd. Defaults to \"ite\".", 0},
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{ "verbose", OPT_VERBOSE, nullptr, 0,
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"verbose mode", -1 },
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{ "verify", OPT_VERIFY, nullptr, 0,
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"verifies the strategy or (if demanded) aiger against the spec.", -1 },
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"Other options further "
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"refine the encoding, see aiger::encode_bdd. Defaults to \"ite\".", 0 },
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{ "dot", OPT_DOT, "options", OPTION_ARG_OPTIONAL,
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"Use dot format when printing the result (game, strategy, or "
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"AIG circuit, depending on other options). The options that "
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"may be passed to --dot depend on the nature of what is printed. "
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"For games and strategies, standard automata rendering "
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"options are supported (e.g., see ltl2tgba --dot). For AIG circuit, "
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"use (h) for horizontal and (v) for vertical layouts.", 0 },
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{ "csv", OPT_CSV, "[>>]FILENAME", OPTION_ARG_OPTIONAL,
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"output statistics as CSV in FILENAME or on standard output "
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"(if '>>' is used to request append mode, the header line is "
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"not output)", 0 },
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{ "hide-status", OPT_HIDE, nullptr, 0,
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"Hide the REALIZABLE or UNREALIZABLE line. (Hint: exit status "
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"is enough of an indication.)", 0 },
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/**************************************************/
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{ nullptr, 0, nullptr, 0, "Miscellaneous options:", -1 },
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{ "extra-options", 'x', "OPTS", 0,
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"fine-tuning options (see spot-x (7))", 0 },
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{ "verbose", OPT_VERBOSE, nullptr, 0, "verbose mode", 0 },
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{ "verify", OPT_VERIFY, nullptr, 0,
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"verify the strategy or (if demanded) AIG against the formula", 0 },
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{ nullptr, 0, nullptr, 0, nullptr, 0 },
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};
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@ -162,8 +174,10 @@ static const char* opt_print_hoa_args = nullptr;
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static bool opt_real = false;
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static bool opt_do_verify = false;
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static const char* opt_print_aiger = nullptr;
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static const char* opt_dot_arg = nullptr;
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static bool opt_dot = false;
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static spot::synthesis_info* gi;
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static bool show_status = true;
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static char const *const algo_names[] =
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{
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@ -254,6 +268,17 @@ namespace
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return s;
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};
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static void
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dispatch_print_hoa(const spot::const_twa_graph_ptr& game)
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{
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if (opt_dot)
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spot::print_dot(std::cout, game, opt_print_hoa_args);
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else if (opt_print_pg)
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spot::print_pg(std::cout, game);
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else
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spot::print_hoa(std::cout, game, opt_print_hoa_args) << '\n';
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}
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static void
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print_csv(const spot::formula& f, const char* filename = nullptr)
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{
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@ -326,7 +351,7 @@ namespace
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outf.close(opt_csv);
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}
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int
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static int
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solve_formula(const spot::formula& f,
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const std::vector<std::string>& input_aps,
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const std::vector<std::string>& output_aps)
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@ -397,15 +422,8 @@ namespace
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std::vector<spot::mealy_like> mealy_machines;
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auto print_game = want_game ?
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[](const spot::twa_graph_ptr& game)->void
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{
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if (opt_print_pg)
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spot::print_pg(std::cout, game);
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else
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spot::print_hoa(std::cout, game, opt_print_hoa_args) << '\n';
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}
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:
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[](const spot::twa_graph_ptr&)->void{};
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[](const spot::twa_graph_ptr& game)->void { dispatch_print_hoa(game); }
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: [](const spot::twa_graph_ptr&)->void{};
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for (; sub_f != sub_form.end(); ++sub_f, ++sub_o)
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{
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@ -425,7 +443,8 @@ namespace
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{
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case spot::mealy_like::realizability_code::UNREALIZABLE:
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{
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std::cout << "UNREALIZABLE" << std::endl;
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if (show_status)
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std::cout << "UNREALIZABLE" << std::endl;
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safe_tot_time();
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return 1;
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}
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@ -448,7 +467,8 @@ namespace
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continue;
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if (!spot::solve_game(arena, *gi))
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{
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std::cout << "UNREALIZABLE" << std::endl;
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if (show_status)
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std::cout << "UNREALIZABLE" << std::endl;
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safe_tot_time();
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return 1;
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}
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@ -506,7 +526,8 @@ namespace
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return 0;
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}
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std::cout << "REALIZABLE" << std::endl;
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if (show_status)
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std::cout << "REALIZABLE" << std::endl;
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if (opt_real)
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{
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safe_tot_time();
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@ -545,7 +566,10 @@ namespace
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<< " latches and "
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<< saig->num_gates() << " gates\n";
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}
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spot::print_aiger(std::cout, saig) << '\n';
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if (opt_dot)
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spot::print_dot(std::cout, saig, opt_dot_arg);
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else
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spot::print_aiger(std::cout, saig) << '\n';
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}
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else
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{
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@ -784,10 +808,7 @@ namespace
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}
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if (opt_print_pg || opt_print_hoa)
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{
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if (opt_print_pg)
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spot::print_pg(std::cout, arena);
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else
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spot::print_hoa(std::cout, arena, opt_print_hoa_args) << '\n';
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dispatch_print_hoa(arena);
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return 0;
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}
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auto safe_tot_time = [&]() {
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@ -796,13 +817,15 @@ namespace
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};
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if (!spot::solve_game(arena, *gi))
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{
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std::cout << "UNREALIZABLE" << std::endl;
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if (show_status)
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std::cout << "UNREALIZABLE" << std::endl;
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safe_tot_time();
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return 1;
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}
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if (gi->bv)
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gi->bv->realizable = true;
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std::cout << "REALIZABLE" << std::endl;
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if (show_status)
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std::cout << "REALIZABLE" << std::endl;
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if (opt_real)
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{
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safe_tot_time();
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@ -905,9 +928,17 @@ parse_opt(int key, char *arg, struct argp_state *)
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opt_decompose_ltl = XARGMATCH("--decompose", arg,
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decompose_args, decompose_values);
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break;
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case OPT_DOT:
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opt_dot = true;
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automaton_format_opt = opt_dot_arg = arg;
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automaton_format = Dot;
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break;
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case OPT_FROM_PGAME:
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jobs.emplace_back(arg, job_type::AUT_FILENAME);
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break;
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case OPT_HIDE:
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show_status = false;
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break;
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case OPT_INPUT:
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{
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all_input_aps.emplace(std::vector<std::string>{});
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@ -7,19 +7,19 @@
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* Basic usage
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This tool synthesizes controllers from LTL/PSL formulas.
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This tool synthesizes reactive controllers from LTL/PSL formulas.
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Consider a set $I$ of /input/ atomic propositions, a set $O$ of output atomic
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propositions, and a PSL formula \phi over the propositions in $I \cup O$. A
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=controller= realizing \phi is a function $c: (2^{I})^\star \times 2^I \mapsto
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*reactive controller* realizing \phi is a function $c: (2^{I})^\star \times 2^I \mapsto
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2^O$ such that, for every \omega-word $(u_i)_{i \in N} \in (2^I)^\omega$ over
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the input propositions, the word $(u_i \cup c(u_0 \dots u_{i-1}, u_i))_{i \in
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N}$ satisfies \phi.
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If a controller exists, then one with finite memory exists. Such controllers
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are easily represented as automata (or more specifically as I/O automata or
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transducers). In the automaton representing the controller, the acceptance
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condition is irrelevant and trivially true.
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If a reactive controller exists, then one with finite memory
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exists. Such controllers are easily represented as automata (or more
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specifically as Mealy machines). In the automaton representing the
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controller, the acceptance condition is irrelevant and trivially true.
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=ltlsynt= has three mandatory options:
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- =--ins=: a comma-separated list of input atomic propositions;
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@ -27,45 +27,52 @@ condition is irrelevant and trivially true.
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- =--formula= or =--file=: a specification in LTL or PSL.
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One of =--ins= or =--outs= may be omitted, as any atomic proposition not listed
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as input can be assumed to be an output and vice-versa.
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as input can be assumed to be output and vice-versa.
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The following example illustrates the synthesis of a controller acting as an
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=AND= gate. We have two inputs =a= and =b= and one output =c=, and we want =c=
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to always be the =AND= of the two inputs:
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The following example illustrates the synthesis of a controller
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ensuring that input =i1= and =i2= are both true initially if and only
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if eventually output =o1= will go from true to false at some point.
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Note that this is an equivalence, not an implication.
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#+NAME: example
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#+BEGIN_SRC sh :exports both
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ltlsynt --ins=a,b -f 'G (a & b <=> c)'
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ltlsynt --ins=i1,i2 -f '(i1 & i2) <-> F(o1 & X(!o1))'
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#+END_SRC
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#+RESULTS: example
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#+begin_example
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REALIZABLE
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HOA: v1
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States: 1
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States: 3
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Start: 0
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AP: 3 "a" "b" "c"
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AP: 3 "i1" "i2" "o1"
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acc-name: all
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Acceptance: 0 t
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properties: trans-labels explicit-labels state-acc deterministic
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controllable-AP: 2
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--BODY--
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State: 0
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[!0&!2 | !1&!2] 0
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[0&1&2] 0
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[0&1&2] 1
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[!0&2 | !1&2] 2
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State: 1
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[!2] 0
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State: 2
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[2] 2
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--END--
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#+end_example
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The output is composed of two parts:
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- the first one is a single line =REALIZABLE= or =UNREALIZABLE;=
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- the second one, only present in the =REALIZABLE= case is an automaton describing the controller.
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In this example, the controller has a single
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state, with two loops labeled by =a & b & c= and =(!a | !b) & !c=.
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- The first one is a single line =REALIZABLE= or =UNREALIZABLE=; the presence of this
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line, required by the [[http://http://www.syntcomp.org/][SyntComp competition]], can be disabled with option =--hide-status=.
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- The second one, only present in the =REALIZABLE= case, is an automaton describing the controller.
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The controller contains the line =controllable-AP: 2=, which means that this automaton
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should be interpreted as a Mealy machine where =o0= is part of the output.
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Using the =--dot= option, makes it easier to visualize this machine.
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#+NAME: exampledot
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#+BEGIN_SRC sh :exports none :noweb yes
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sed 1d <<EOF | autfilt --dot=.A
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<<example()>>
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EOF
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#+BEGIN_SRC sh :exports code
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ltlsynt --ins=i1,i2 -f '(i1 & i2) <-> F(o1 & X(!o1))' --hide-status --dot
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#+END_SRC
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#+BEGIN_SRC dot :file ltlsyntex.svg :var txt=exampledot :exports results
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@ -75,9 +82,6 @@ EOF
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#+RESULTS:
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[[file:ltlsyntex.svg]]
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The label =a & b & c= should be understood as: "if the input is =a&b=,
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the output should be =c=".
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The following example illustrates the case of an unrealizable specification. As
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=a= is an input proposition, there is no way to guarantee that it will
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eventually hold.
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@ -90,11 +94,68 @@ ltlsynt --ins=a -f 'F a'
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: UNREALIZABLE
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By default, the controller is output in HOA format, but it can be
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output as an [[http://fmv.jku.at/aiger/][AIGER]] circuit thanks to the =--aiger= flag. This is the
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output format required for the [[http://syntcomp.org/][SYNTCOMP]] competition.
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output as an And-Inverter-Graph in [[http://fmv.jku.at/aiger/][AIGER format]] using the =--aiger=
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flag. This is the output format required for the [[http://syntcomp.org/][SYNTCOMP]] competition.
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The generation of a controller can be disabled with the flag =--realizability=.
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In this case, =ltlsynt= output is limited to =REALIZABLE= or =UNREALIZABLE=.
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#+NAME: exampleaig
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#+BEGIN_SRC sh :exports both
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ltlsynt --ins=i1,i2 -f '(i1 & i2) <-> F(o1 & X(!o1))' --aiger
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#+END_SRC
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#+RESULTS: exampleaig
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#+begin_example
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REALIZABLE
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aag 14 2 2 1 10
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2
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4
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6 14
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8 29
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7
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10 7 9
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12 4 10
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14 2 12
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16 7 8
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18 4 16
|
||||
20 5 7
|
||||
22 21 19
|
||||
24 2 23
|
||||
26 3 7
|
||||
28 27 25
|
||||
i0 i1
|
||||
i1 i2
|
||||
o0 o1
|
||||
#+end_example
|
||||
|
||||
The above format is not very human friendly. Again, by passing both
|
||||
=--aiger= and =--dot=, one can display the And-Inverter-Graph representing
|
||||
the controller:
|
||||
|
||||
#+NAME: exampleaigdot
|
||||
#+BEGIN_SRC sh :exports code
|
||||
ltlsynt --ins=i1,i2 -f '(i1 & i2) <-> F(o1 & X(!o1))' --hide-status --aiger --dot
|
||||
#+END_SRC
|
||||
|
||||
#+BEGIN_SRC dot :file ltlsyntexaig.svg :var txt=exampleaigdot :exports results
|
||||
$txt
|
||||
#+END_SRC
|
||||
|
||||
#+RESULTS:
|
||||
[[file:ltlsyntexaig.svg]]
|
||||
|
||||
In the above diagram, round nodes represent AND gates. Small black
|
||||
circles represent inversions (or negations), colored triangles are
|
||||
used to represent input signals (at the bottom) and output signals (at
|
||||
the top), and finally rectangles represent latches. A latch is a one
|
||||
bit register that delays the signal by one step. Initially, all
|
||||
latches are assumed to contain =false=, and them emit their value from
|
||||
the =L0_out= and =L1_out= rectangles at the bottom. Their input value,
|
||||
to be emitted at the next step, is received via the =L0_in= and =L1_in=
|
||||
boxes at the top. In =ltlsynt='s encoding, the set of latches is used
|
||||
to keep track of the current state of the Mealy machine.
|
||||
|
||||
The generation of a controller can be disabled with the flag
|
||||
=--realizability=. In this case, =ltlsynt='s output is limited to
|
||||
=REALIZABLE= or =UNREALIZABLE=.
|
||||
|
||||
* TLSF
|
||||
|
||||
|
|
@ -177,7 +238,18 @@ be tried by separating them using commas. For instance
|
|||
You can also ask =ltlsynt= to print to obtained parity game into
|
||||
[[https://github.com/tcsprojects/pgsolver][PGSolver]] format, with the flag =--print-pg=, or in the HOA format,
|
||||
using =--print-game-hoa=. These flag deactivate the resolution of the
|
||||
parity game.
|
||||
parity game. Note that if any of those flag is used with =--dot=, the game
|
||||
will be printed in the Dot format instead:
|
||||
|
||||
#+NAME: examplegamedot
|
||||
#+BEGIN_SRC sh :exports code
|
||||
ltlsynt --ins=i1,i2 -f '(i1 & i2) <-> F(o1 & X(!o1))' --print-game-hoa --dot
|
||||
#+END_SRC
|
||||
#+BEGIN_SRC dot :file ltlsyntexgame.svg :var txt=examplegamedot :exports results
|
||||
$txt
|
||||
#+END_SRC
|
||||
#+RESULTS:
|
||||
[[file:ltlsyntexgame.svg]]
|
||||
|
||||
For benchmarking purpose, the =--csv= option can be used to record
|
||||
intermediate statistics about the resolution.
|
||||
|
|
@ -200,6 +272,11 @@ Further improvements are described in the following paper:
|
|||
/Alexandre Duret-Lutz/, and /Adrien Pommellet/. Presented at the
|
||||
SYNT'21 workshop. ([[https://www.lrde.epita.fr/~adl/dl/adl/renkin.21.synt.pdf][pdf]] | [[https://www.lrde.epita.fr/~adl/dl/adl_bib.html#renkin.21.synt][bib]])
|
||||
|
||||
Simplification of Mealy machines is discussed in:
|
||||
|
||||
- *Effective reductions of Mealy machines*, /Florian Renkin/,
|
||||
/Philipp Schlehuber-Caissier/, /Alexandre Duret-Lutz/, and /Adrien Pommellet/.
|
||||
Presented at FORTE'22. ([[https://www.lrde.epita.fr/~adl/dl/adl/renkin.22.forte.pdf][pdf]] | [[https://www.lrde.epita.fr/~adl/dl/adl_bib.html#renkin.22.forte][bib]])
|
||||
|
||||
# LocalWords: utf ltlsynt AIGER html args mapsto SRC acc aiger TLSF
|
||||
# LocalWords: UNREALIZABLE unrealizable SYNTCOMP realizability Proc
|
||||
|
|
|
|||
|
|
@ -985,3 +985,22 @@ ltlsynt -f "G(o1|o2) & (GFi <-> GFo1)" --outs="o1,o2" --verbose\
|
|||
--bypass=yes 2> out
|
||||
sed 's/ [0-9.e-]* seconds/ X seconds/g' out > outx
|
||||
diff outx exp
|
||||
|
||||
# Test --dot and --hide-status
|
||||
ltlsynt -f 'i <-> Fo' --ins=i --aiger --dot | grep arrowhead=dot
|
||||
ltlsynt -f 'i <-> Fo' --ins=i --print-game-hoa --dot | grep 'shape="diamond"'
|
||||
ltlsynt -f 'i <-> Fo' --ins=i --dot --hide-status > res
|
||||
cat >exp <<EOF
|
||||
digraph "" {
|
||||
rankdir=LR
|
||||
node [shape="circle"]
|
||||
I [label="", style=invis, width=0]
|
||||
I -> 0
|
||||
0 [label="0"]
|
||||
0 -> 0 [label="i / o"]
|
||||
0 -> 1 [label="!i / !o"]
|
||||
1 [label="1"]
|
||||
1 -> 1 [label="1 / !o"]
|
||||
}
|
||||
EOF
|
||||
diff res exp
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue