Aiger circuits noew have their own class.
Monitors can be translated to and obtained
from aiger circuits.
Moreover a step by step evaluation method
is provided.
* spot/twaalgos/aiger.hh,
spot/twaalgos/aiger.cc: Here
* bin/ltlsynt.cc: Adopt new modes
* tests/core/ltlsynt.test: Adapt tests
* python/spot/impl.i: Add python support
* tests/Makefile.am,
tests/python/aiger.py: New test cases
* spot/twa/twagraph.cc: Implement it.
* spot/twa/twagraph.hh, NEWS: Document it.
* tests/python/mergedge.py: Test it.
* tests/core/ltlsynt.test, tests/python/games.ipynb: Adjust expectations.
Also have simul-max default to 4096 instead of 512, because it's
really simul-trans-pruning that is very slow and need to be limited.
* spot/twaalgos/postproc.cc, spot/twaalgos/postproc.hh,
spot/twaalgos/simulation.cc, spot/twaalgos/simulation.hh,
spot/twaalgos/determinize.cc, spot/twaalgos/determinize.hh:
Implement the above options.
* bin/spot-x.cc, NEWS: Document them.
* tests/core/ltlsynt.test, tests/core/minusx.test,
tests/core/sim3.test: Add some test cases.
This fixes#452, and also fix a bug related to transiant SCCs
incorrectly merged in cosimulation: the source of the edges was
updated without fixing the chaining of the edges.
* spot/twaalgos/simulation.cc: Fix all the above.
* tests/python/simstate.py: Add test case from issue #452.
* tests/core/det.test, tests/core/ltlsynt.test,
tests/core/satmin.test: Lower expected sizes.
* tests/python/decompose.ipynb: Adjust for changed order.
Related to issue #298.
* spot/twaalgos/determinize.cc: Recognize braces that are temporary
to avoid emitting colors when they become empty.
* tests/python/298.py: New file, showing a reduction of colors.
* tests/Makefile.am: Add it.
* tests/core/ltlsynt.test: Adjust expected output (now smaller).
* tests/core/genltl.test: Adjust one expected output (now larger).
* NEWS: Mention the issue.
* spot/twaalgos/synthesis.cc, spot/twaalgos/synthesis.hh: New files
regrouping the functionnalities split and apply_strategy for synthesis
* python/spot/impl.i, spot/twaalgos/Makefile.am: Add them.
* spot/twaalgos/split.cc, spot/twaalgos/split.hh: No longer contains
the splits necessary for for synthesis, moved to
spot/twaalgos/synthesis.cc, spot/twaalgos/split.hh Split is now faster
and reduces the number of intermediate states, reducing the overall
size of the arena
* spot/misc/game.cc, spot/misc/game.hh: Renaming propagate_players to
alternate_players.
* tests/core/ltlsynt.test, tests/python/split.py: Update tests.
* bin/ltlsynt.cc: Adjust to new split. Swap order of split and
to_parity for lar.
* spot/misc/game.cc, spot/misc/game.hh: More efficient implementation
of Zielonka's algorithm to solve parity games. Now supports SCC
decomposition and efficient handling of certain special cases.
* doc/org/concepts.org: Document "strategy" and "state-winner"
properties.
* bin/ltlsynt.cc, tests/python/paritygame.ipynb: Adjust.
* tests/core/ltlsynt.test: Add more tests.
* spot/twaalgos/aiger.cc, spot/twaalgos/aiger.hh: Reimplement
print_aiger for speed gain, also heuristics to minimize the number
of gates as well as different encoding types have been added.
* bin/ltlsynt.cc: Make the new options for print-aiger available.
* tests/core/ltlsynt.test: Adjust tests.
* bin/ltlsynt.cc (complete_env): Replace this function by...
* spot/misc/game.hh, spot/misc/game.cc (propagate_players): ... this
new one, hiding the "state-player" business from ltlsynt. Also do not
create a sink states unless necessary.
* tests/core/ltlsynt.test: Adjust expected number of states.
* spot/tl/simplify.hh, spot/tl/simplify.cc,
spot/twaalgos/translate.cc: Update the tl_simplification
options after all preferences have been given.
* bin/ltlsynt.cc: Display the size of the translation output.
* tests/core/ltlsynt.test: Add test case.
* bin/ltlsynt.cc: Make sure to_parity_old() receive a deterministic
automaton, for correctness. Also call reduce_parity() afterward,
to match what was done in 2.8.7.
* tests/core/ltlsynt.test: Include lar.old in the comparison of all
results to make sure it give the same result as the other 3
algorithms.
* spot/twaalgos/aiger.cc: Simplify some bit operatitions. Force the
ordering of operations in aig_and, that was causing a test case to
fail on ARM, and greatly simplify the code and data structures used in
remove_unused().
* tests/core/ltlsynt.test: Adjust expected output.
ltlsynt now offers two algorithms: one where splitting occurs before
determinization (the historical one) and one where determinization
occurs before splitting.
* bin/ltlsynt.cc: here
* tests/core/ltlsynt.test: test it and refactor test file
* NEWS: document it
* spot/misc/game.hh, spot/misc/game.cc: remove Calude's algorithm
Improve the way transitions are duplicated when preparing the turn-based
game for synthesis. The resulting arena should now be deterministic on
nodes owned by the environment. Also move the code to another file, so
that it is easier to test (e.g. in Python).
* bin/ltlsynt.cc: move the code
* spot/twaalgos/split.cc, spot/twaalgos/split.hh: move the code and
implement the improvements
* tests/Makefile.am, tests/python/split.py: test it
* tests/core/ltlsynt.test: update existing tests to reflect the changes
To ease debugging and testing, ltlsynt can output the synthesized
strategy as an automaton, not just an aiger circuit.
Also, its exit code has been changed to something meaningful.
* bin/ltlsynt.cc: Various improvements: options, exit code, code style
* spot/twaalgos/aiger.hh, spot/twaalgos/aiger.cc,
spot/twaalgos/Makefile.am: Move the aiger printer to separate files
* tests/core/ltlsynt.test: Clean up and update test file
* tests/Makefile.am: Add the test file to the test suite
* NEWS: document the new aiger printer
* doc/org/concepts.org: document the named property "synthesis-outputs",
used by print_aiger
