To ease debugging and testing, ltlsynt can output the synthesized
strategy as an automaton, not just an aiger circuit.
Also, its exit code has been changed to something meaningful.
* bin/ltlsynt.cc: Various improvements: options, exit code, code style
* spot/twaalgos/aiger.hh, spot/twaalgos/aiger.cc,
spot/twaalgos/Makefile.am: Move the aiger printer to separate files
* tests/core/ltlsynt.test: Clean up and update test file
* tests/Makefile.am: Add the test file to the test suite
* NEWS: document the new aiger printer
* doc/org/concepts.org: document the named property "synthesis-outputs",
used by print_aiger
This also fixes some empty lines and unsorted options
that appeared in some tools.
* tests/sanity/bin.test: Ensure this is done.
* bin/README: Add a new paragraph about this.
* bin/autcross.cc, bin/ltlcross.cc: Move the
output options in their own section.
* bin/common_color.cc: Assume color options are
in group -15.
* bin/common_finput.cc, bin/common_finput.hh:
Add a headless variant.
* bin/genltl.cc, bin/ltlfilt.cc, bin/ltlgrind.cc,
bin/randaut.cc, bin/randltl.cc: Do not force the
children groups, so that the options are correctly sorted.
* bin/ltlsynt.cc: Add missing groups.
* spot/misc/game.cc, spot/misc/game.hh: Here.
* bin/ltlsynt.cc: Realizability is now done by checking if the winning
strategy contains the initial state.
For now, ltlsynt only handles LTL realizability. It uses a reduction to
parity game followed by Calude et al.'s reduction from parity game to
reachability game.
* bin/ltlsynt.cc, bin/Makefile.am, bin/man/ltlsynt.x,
bin/man/Makefile.am, bin/.gitignore: New binary.
* doc/org/arch.tex, doc/Makefile.am, doc/org/tools.org,
doc/org/ltlsynt.org: Document it.
* spot/misc/game.cc, spot/misc/game.hh, spot/misc/Makefile.am: Parity
game wrapper for parity automata + reachability game interface from
Calude et al.'s paper.
